You should read the manual of formailty, this is becase dff synthesis to two latch structure. So you should tell formailty how to deal with it .And i use conform, about this , command like:
set flatten model -latch_fold.
you can find some command like this at the manual of formailty
Added after 3 minutes:
Or anther answer is gate clock, synthesis add some latch to control gate clock , we should control those latch as gate , at conform :
set flatten model -latch_transparent.