Help: what is wrong with my verilog code?

[jordan76]

Hi

In the following verilgo code,I want to generate a register with a RESET terminal and a PRESET terminal. But the simulation results show that it did not meet my requirements.

Could anyone help me out?
Thanks in advance!

regards,
jordan76

//define a register
reg out_en;

always @(posedge clk or negedge reset_b or negedge preset_b)
begin
if (!reset_b)
out_en<=1'b0;
else if (!preset_b)
out_en<=1'b1;
else if (condition A) // if condition A is true
out_en<=1'b0;
else if (condition B) // if condition B is true
out_en<1'b1;
end

 

[jelydonut]

it seems to look ok.. other than you need alot more begin and ends..
especially for your else clocking conditions

always @(posedge clk or negedge reset_b or negedge preset_b)
if (~reset_b)
out_en<=1'b0;
else
begin
if (~preset_b)
out_en<=1'b1;
else
begin
if (condition A) // if condition A is true
out_en<=1'b0;
else
if (condition B) // if condition B is true
out_en<1'b1;
end
end

jelydonut

ps.. it would be alot easier to look at it if it didn't remove the begining spacing for each line..

 

[jelydonut]

oh.. also.. when simulating your set/clr conditions will appear to act as clocks and will only occur on the edges.. they won't simulate as a async set/clr.. so.. if you had a your set condition asserted and a clk came in then the always block will still be executed regardless of the set condition... normally its not a issue.. but i've had it effect me before..

jelydonut

 

[claint]

simulation results should be ok, but you should note the time relationship of the async reset and preset signals and the edge of the clock. Actually,I
suggest that you change the async preset to synchronous preset.Because many libs don't have both async reset and preset signals .

 

[gerade]

if I am not wrong, verilog is not possible to describle a FF with RN and SN.

 

[always@smart]

simulation results should be ok, but you should note the time relationship of the async reset and preset signals and the edge of the clock. Actually,I
suggest that you change the async preset to synchronous preset.Because many libs don't have both async reset and preset signals .

---------------------------------------------------------------------------------

i agree with claint suggestion. Please check the libs and ensure there is an asychronous preset.

or maybe u can change ur code in this way:

always @(posedge clk or negedge reset_b or negedge preset_b)
begin
if (!reset_b)
out_en<=1'b0;
else if (!preset_b)
out_en<=1'b1;
else begin
if (condition A) // if condition A is true
out_en<=1'b0;
else if (condition B) // if condition B is true
out_en<1'b1;
end
end

hope it helps!!!

--always@smart

 

[jordan76]

All of you,
Thanks for your kind help and suggestions!

Actually I need both an asyn RESET_B and an asyn PRESET_B for my
case and RESET_B has the highest priority of execution.

To avoid a FF with RN and SN,I rewrite the code in the following way:

reg outen_mw_temp;
wire outen_mw;

always @(posedge clk or negedge preset_b)
begin
if (!preset_b)
out_en_temp<=1'b1;
else
begin
if (condition A) // if condition A is true
out_en_temp<=1'b0;
else if (condition B) // if condition B is true
out_en_temp<1'b1;
end
end

assign outen_mw=outen_mw_temp & reset_b;

The simulation results seems OK. Any comment on that?

Thanks again!

regards,
jordan76

 

[z81203]

To avoid a FF with RN and SN,I rewrite the code in the following way:

reg outen_mw_temp;
wire outen_mw;

always @(posedge clk or negedge preset_b)
begin
if (!preset_b)
out_en_temp<=1'b1;
else
begin
if (condition A) // if condition A is true
out_en_temp<=1'b0;
else if (condition B) // if condition B is true
out_en_temp<1'b1;
end
end

assign outen_mw=outen_mw_temp & reset_b;

The simulation results seems OK. Any comment on that?

hi, are you synthesis it? dies it meet? could you tell me the result of synthesis?
thx.

 

[jordan76]

hi, are you synthesis it? dies it meet? could you tell me the result of synthesis?
thx.

z81203 and all,

The synthesis result is OK. Thanks a lot!

regards,
jordan76