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Help! VHDL for a matrix multiplier using a Multiply-Accumulate (MAC) unit

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The A and B matrices should implement have 4x5 and 5x3 dimensions.. It has to pipelined and parallel.

1) Implement the code with integer type signals with test bench.
2) Implement the code with std_logic_vector type signals with test bench.

I understand the logic for this code but I have no clue on how to code it. :???:
 

why would you use std_logic_vectors - they are not numbers - what a pain in the arse to do all the type conversions.

I suspect this is homework. I suggest having a go yourself, and asking specific questions, rather than "I dont understand, please do my homework for me".
 

Well, I've made my matrices to multiply. I have no idea how to add to accumulate (register?) and make it parallel and pipelined.

The parallel and pipeline thing confuses me, because now I don't think I made the matrices correctly since I only made it to multiply with an output of 4x3
 

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