library ieee;
use ieee.std_logic_1164.all;
entity updowncounter is
generic (n: natural := 8);
port ( IC,CLK,upcount,downcount :in std_logic ;
Q: out std_logic_vector(n-1 downto 0) );
end updowncounter ;
architecture exm1 of updowncounter is
begin
prc:process (IC,CLK) is
variable cnt : unsigned (n-1 downto 0); -- the unsigned variable ca take + operation unlike standard logic vector;;;
begin
if IC= '1' then cnt:= (others=> '0');
elsif rising_edge (CLK ) and upcount = '1' then cnt:= cnt + 1;
elsif rising_edge (CLK) and downcount='1' then cnt:= cnt - 1 ;
end if ;
end process prc;
end exm1;