[SOLVED] Help to understand SDRAM block diagram

[prcken]

HI,
I am not sure if it's the right place to ask this question.
Could anyone help me to understand the block diagram that i attached below?

I got it from this link

I couldn't understand the "16,384 x 256 x 32" in the bank, seems 2^14 WLs, 2^8 BLs, but what does 32 mean? is that 32 sub array?
I think the key issue is i don't know how does I/O gating DM mask logic work, and how does the FIFO transfers 32-bit into 4-bit?

Can anybody help?
Thanks!

 

[TrickyDicky]

That will be 16384 rows x 256 columns x 32 bit words (4 bytes). With 8 banks of that.

 

[prcken]

That will be 16384 rows x 256 columns x 32 bit words (4 bytes). With 8 banks of that.

thanks, how to understand 32 bit words here in terms of array in one bank?
it has 256 x 32 sense amplifiers, does that mean it has 256 x 32 Bit lines?

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usually we say by selecting one Row address and one column address to access one bit cell, only one cell active at the bit line. now, it seems by choosing one row address and one column address can access 32 bit cells, in that case, it needs 32 BLs.
how to do that?

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32 sub array in one bank?

 

[TrickyDicky]

32 bit words is very standard. there will be 32 data lines out of the chip.

 

[prcken]

32 bit words is very standard. there will be 32 data lines out of the chip.

thanks. i think we are talking different things. i am looking it at a lower physical memory topology level. you are saying it at a higher level.
actually, in this case, four I/Os out from this chip, it is 32-bits go into the FIFO, then do MUX, 4 go out of the chip.