help script dc_shell-t

[ouahhabi5]

dc_shell versus dc_shell-t

I know that is a stupid question but I am just a bigginer in this thinks,
I want write a script by tcl language that actions :
-Reset design
-ceation the clock
-force the inputs port except the port clk
-force the outputs port
-adopt the operating conditions which are to specify in the technological bookshop
-Automatic selection of the wire_load_model
- define the driving_cell on inputs (except clk)
-define the maximum capacitance on the inputs port
-define the capacitive load on the outputs port


the spefications are :
-Frequency of clock 200 Mhz (5ns)
-Operating condition wc représenté de la libraire core_slow.db(1.62V,125°C)
-Wire_load_model Automatic selection
-Constraints on the inputs 80% of clock period
-Constraints on the output 20% of clock period
-Cell feeding the inputs « f de f 1 a 1 » pin « Q »
-Capacitance max on the inputs 5 « and 2 a 1 » pin « A »
-A number of blocks supplied with the outputs 3


I just wrote this lignes:
reset_design
create_clock -period 5 -name myclk [get_ports Clk]
set_input_delay 1 –max -clock myclk [remove_from_collection [all_ inputs] [get_ports Clk]]
set_output_delay 1 -max


tell me plz if it is correct, and i need some helps to continue the script thanks for everybody

 

[nand_gates]

Here it goes Its from DC training material!
DC traininng material is a good reference while you write ur scripts!

# Create user defined variables
set CLK_PORT [get_ports Clk]
set CLK_PERIOD 4.0
set WC_SKEW 0.25
set DRV_CELL buf1a3
set DRV_PIN "Y"
set OUTPUT_LOAD [load_of ssc_core_slow/buf1a2/A]
set INPUT_DELAY 2.0
set OUTPUT_DELAY 2.0
set ALL_INS_EX_CLK \
    [remove_from_collection [all_inputs] [get_ports Clk]]


# Start with an unconstrainted design
reset_design

set_operating_conditions -max slow_125_1.62

create_clock -period $CLK_PERIOD -name my_clk $CLK_PORT

set_dont_touch_network [get_clocks my_clk]

set_clock_uncertainty $WC_SKEW [get_clocks my_clk]

set_driving_cell -lib_cell $DRV_CELL -pin $DRV_PIN $ALL_INS_EX_CLK

set_load $OUTPUT_LOAD [all_outputs]

set_input_delay $INPUT_DELAY -max -clock my_clk $ALL_INS_EX_CLK

set_output_delay $OUTPUT_DELAY -max -clock my_clk [all_outputs]

 

[ouahhabi5]

this is a very great help from you nand_gates thanks you very much realy i dont know what can i do without this forum.
plz nand_gates can you tell more about DC training material and if you have it can you give it to me. thank you again and again[/img]