ouahhabi5
Newbie level 6
dc_shell versus dc_shell-t
I know that is a stupid question but I am just a bigginer in this thinks,
I want write a script by tcl language that actions :
-Reset design
-ceation the clock
-force the inputs port except the port clk
-force the outputs port
-adopt the operating conditions which are to specify in the technological bookshop
-Automatic selection of the wire_load_model
- define the driving_cell on inputs (except clk)
-define the maximum capacitance on the inputs port
-define the capacitive load on the outputs port
the spefications are :
-Frequency of clock 200 Mhz (5ns)
-Operating condition wc représenté de la libraire core_slow.db(1.62V,125°C)
-Wire_load_model Automatic selection
-Constraints on the inputs 80% of clock period
-Constraints on the output 20% of clock period
-Cell feeding the inputs « f de f 1 a 1 » pin « Q »
-Capacitance max on the inputs 5 « and 2 a 1 » pin « A »
-A number of blocks supplied with the outputs 3
I just wrote this lignes:
reset_design
create_clock -period 5 -name myclk [get_ports Clk]
set_input_delay 1 –max -clock myclk [remove_from_collection [all_ inputs] [get_ports Clk]]
set_output_delay 1 -max
tell me plz if it is correct, and i need some helps to continue the script thanks for everybody
I know that is a stupid question but I am just a bigginer in this thinks,
I want write a script by tcl language that actions :
-Reset design
-ceation the clock
-force the inputs port except the port clk
-force the outputs port
-adopt the operating conditions which are to specify in the technological bookshop
-Automatic selection of the wire_load_model
- define the driving_cell on inputs (except clk)
-define the maximum capacitance on the inputs port
-define the capacitive load on the outputs port
the spefications are :
-Frequency of clock 200 Mhz (5ns)
-Operating condition wc représenté de la libraire core_slow.db(1.62V,125°C)
-Wire_load_model Automatic selection
-Constraints on the inputs 80% of clock period
-Constraints on the output 20% of clock period
-Cell feeding the inputs « f de f 1 a 1 » pin « Q »
-Capacitance max on the inputs 5 « and 2 a 1 » pin « A »
-A number of blocks supplied with the outputs 3
I just wrote this lignes:
reset_design
create_clock -period 5 -name myclk [get_ports Clk]
set_input_delay 1 –max -clock myclk [remove_from_collection [all_ inputs] [get_ports Clk]]
set_output_delay 1 -max
tell me plz if it is correct, and i need some helps to continue the script thanks for everybody