Help!! Ref Clock harmonic Interference to RF receiver IF path!

[poorren]

Hello folks,
I'm trying to build a homebrew RF receiver board. The receiver is of 2 stage down-converter schema. The first IF SAW filter of that receiver is selected to 190Mhz center frequency. In actual measurement the 2IF output, I found a Spur in middle of receiver passband. With some experiments, I found the spur is due to the harmonic product of reference clock of RF board at 190Mhz!!!

The receiver board used an external Ref clock 10Mhz. The clock is buffered and distributed with a simple 74AC04 chip(around 2.5Vpp). When doing the layout of this area, all the Ref clock signal wires are buried in mid layer of PCB (between two Ground layers) with ground vias around to construct a wall. And the placement of Ref clock is far from receiver IF area. Even using this rigorous layout methodology, I still couldn't prevent the 19th harmonic of ref clock diving into the IF path. Based on the measured Spur power at 3IF output and receiver IF gain, I could inversely compute the power this 19th harmonic interference is about -115dBm. So, the board layout isolation is larger than 120dB. I once attempt to solve by using a small capacitor 27pF shunt at 74AC04 signal output. Little improvement is achieved. ~~~ However, if I put my finger to touch the 74AC04 pins, the power of 190Mhz spur could be obviously reduced by about 5dB. I couldn't explain what the effect of my finger is.

One thing to note is I don't have a shield box to cover on the RF receiver now. (will be available next week...) But, my doubt now is if this harmonic interference couples by space, or board, or GND. My big concern is even the shield box won't help me much.

I would like to write this post as open questions, and like to hear your ideas and thinking!

Please reply if you think any points. Thanks advance!

Jeff

 

[crutschow]

The harmonics of interest are likely generated by the fast rise-time of the 74AC04. When you touch the output with your finger, you slow the rise-time and reduce the harmonics.

One suggestion is to use a slower logic family such as the 74HC04 for the clock driver. It's slower rise-time should reduce the harmonics.

You could also try placing a small, lossy inductor, such as a ferrite bead, in series with the driver output to reduce the harmonics.

 

[poorren]

The harmonics of interest are likely generated by the fast rise-time of the 74AC04. When you touch the output with your finger, you slow the rise-time and reduce the harmonics.

One suggestion is to use a slower logic family such as the 74HC04 for the clock driver. It's slower rise-time should reduce the harmonics.

You could also try placing a small, lossy inductor, such as a ferrite bead, in series with the driver output to reduce the harmonics.

Hello,
I attempted to place a bead in clock line with small cap 100pF in Shunt. The clock spur is reduced greatly. However, the noise floor is still higher than expected.
In further experiment, I found the path, where the clock spur is picked into receiver, is an short line buried in the middle layer of PCB. If I bypass this line with kludged line in top layer of PCB. The noise floor and spur both get improved.

In this receiver board, I used six layer board stack as below.

RF signal --- Top layer
AGND ---
mid signal ---
AGND ---
PWR ---
control signal --- bottom layer (low frequency, SPI ctrl lines)

Most of receiver RF signal line is placed on top layer. Considering the noisy of clock, I placed the reference clock into mid layer with Vias (conneted to AGND) on both side of clock line. Due to lack enough routine path in top, I have to place several RF analog signal line of receiver in mid layer. The layout scheme is same as clock, with vias on sides of line. One thing to note is I don't place large area AGND copper in spare space of mid layer. I just used vias to construct the isolation wall between them.

The line picked up the clock spur is near the input of IF path. Due to the high gain in IF path, this spur gets amplified, and finally hurts the IF output. With some measurement on the output of 74AC04, the clock power is around 10dBm. The clock spur output at IF output is around -60dBm, the IF path gain is around 35dB. So, the spur picked up by that line is about ~ -95dBm, which means the current layout isolation is around 105dB.

My question is I'm not sure if this could be improved further. I hope!! The choice in my mind is either to place large area AGND copper in mid layer, which occupies the space between signal line and clock line, or to expand the current stack structure to 8 layer, and place the clock in separate layer for best performance. I don't like the idea of 8 layer board, which is much expensive.

So, I'd like hear your voice and suggestion on this. Thanks advance!

Jeff