help reagrding Decimation FIR on FPGA

[haneet]

hello frndz,

I am trying to write a verilog code for Decimation FIR filter. Can any1 tell me how do we select the coefficients??

I did see a hardware structure where the Input is fed to a demux with select line as modulo counter and the output of the demux is connected to the rom each having even and odd coefficients seperated. (I hope i have made things clear)

I understand that the coefficents are to be stored in the Rom but the rest isn't really helping out.

thanks,

Haneet

 

[radar08]

hello

the fir coefficients are decided by factors list below:
1. sample rate;
2. band width of expected signal;
3. decimation factor

you can get some information from GC1012a.pdf which is a userguide of GC1012.

GC1012 is a special DDC(Digital Down Converter) chip.