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[SOLVED] help ! random func in systemverilog

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xpratx

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I wrote this small code to test the values stored in a 2-d array but it is not simulated by VCS. can anyone help??
i am new guy so please point in a specific direction.

module xyz();
reg [31:0] addrmem [31:0]
for ( i=0 ; i<33 ; i++)
begin
addrmem = $random();
end
endmodule
 

ljxpjpjljx

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what do you mean by not simulated by VCS? is there any error?
 

yanzixuan

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I thought it should be like this:
Code:
module xyz();
 reg [31:0] addrmem [31:0]
 
 initial  begin
    for ( i=0 ; i<32 ; i++) 
    begin 
      addrmem[i] = $random();
    end
 end
 endmodule
 
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    xpratx

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xpratx

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cheers man it worked your way.
 

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