[SOLVED] help ! random func in systemverilog

[xpratx]

I wrote this small code to test the values stored in a 2-d array but it is not simulated by VCS. can anyone help??
i am new guy so please point in a specific direction.

module xyz();
reg [31:0] addrmem [31:0]
for ( i=0 ; i<33 ; i++)
begin
addrmem = $random();
end
endmodule

 

[ljxpjpjljx]

what do you mean by not simulated by VCS? is there any error?

 

[yanzixuan]

I thought it should be like this:

module xyz();
 reg [31:0] addrmem [31:0]
 
 initial  begin
    for ( i=0 ; i<32 ; i++) 
    begin 
      addrmem[i] = $random();
    end
 end
 endmodule

 

[xpratx]

cheers man it worked your way.