nicklas_a74
Member level 1
- Joined
- Oct 4, 2002
- Messages
- 37
- Helped
- 8
- Reputation
- 16
- Reaction score
- 7
- Trophy points
- 1,288
- Activity points
- 316
Hi
I want to use embedded psl into a vhdl testbench and force a signal
to e.g. '0' and then unforce it. How to write psl for this? I compile and
simulate my design using modelsim 6.5a. I have seen different syntax for
this but unsure how to get it to work. I dont want to write commands
in modelsim only embed it into the "normal" testbench .vhdl file
--psl ??? <= force '0';
I want to use embedded psl into a vhdl testbench and force a signal
to e.g. '0' and then unforce it. How to write psl for this? I compile and
simulate my design using modelsim 6.5a. I have seen different syntax for
this but unsure how to get it to work. I dont want to write commands
in modelsim only embed it into the "normal" testbench .vhdl file
--psl ??? <= force '0';
