[SOLVED] [HELP] Parallel FIR Filter Structures

[demetal]

hi,


i want to implement a project in vlsi "Parallel FIR Filter Structures With 2-Stage Parallelism" i got this project from a friend and i want to simulate the output using xilinx software ... i have the codings and simulation results .... but i dont know how to simulate the codings because its given in different files in word document .... i am attaching the files necessary to analyse... please help to simulate this project....

 

[TrickyDicky]

Your friend does not have any idea how to code for FPGAs.

 

[demetal]

No..He got it from internet... And i dont even know to simulate this code... I have worked in xilinx basic coding... If you know how... please help...

 

[TrickyDicky]

first of all, copy and past all of the code into a .vhd file (its just a text file).
Secondly, learn how to use a simulator.
3rd. See the results, smile.

4. If you want to put it on an FPGA - delete all the code and re-write everything. This code will not work on an FPGA.

 

[demetal]

Hi dicky,

thanks for your support.... i just want to get the simulation result.....i have combined the two files unto a single one ( the matrix class and main file) and simulated it.....
...but its showing some errors... please help to rectify it.....
here is the code

library ieee;
use ieee.std_logic_1164.all;

package matrix_class is

subtype single is integer;
type logic_4_vector is array (integer range <>) of std_logic_vector(3 downto 0);
type single_vector is array (INTEGER range <>) of single;

function sum_of_products (
lower_limit : INTEGER;
upper_limit : INTEGER;
a_in : single_vector;
b_in : single_vector
) return single;

function shift_fifo (
fifo : single_vector;
data_in : single
) return single_vector;

function reverse_order (table : single_vector) return single_vector;


end matrix_class;

package body matrix_class is

function sum_of_products (
lower_limit : integer;
upper_limit : integer;
a_in : single_vector;
b_in : single_vector
)
return single is
variable partial_sum,running_total,sum : single;
variable a : single_vector(a_in'length-1 downto 0);
variable b : single_vector(b_in'length-1 downto 0);
begin
a := a_in(upper_limit downto lower_limit);
b := b_in(upper_limit downto lower_limit);

running_total := 0;
for i in lower_limit to upper_limit loop
partial_sum := a(i) * b(i);
running_total := running_total + partial_sum;
end loop;
sum := running_total;
return sum ;
end sum_of_products;

function shift_fifo (
fifo : single_vector;
data_in : single
) return single_vector is
variable fifo_out : single;
variable fifo_queue : single_vector(fifo'length-1 downto 0);
variable fifo_element : single;
begin
fifo_queue := fifo(fifo'length-1 downto 0);
fifo_element := data_in;

fifo_out := fifo_queue(fifo_queue'length-1);
for i in fifo_queue'length-1 downto 1 loop
fifo_queue(i) := fifo_queue(i-1);
end loop;
fifo_queue(0) := fifo_element;
return fifo_queue ;
end shift_fifo;

function reverse_order (table : single_vector) return single_vector is
variable original_table : single_vector(table'length-1 downto 0);
variable reversed_table : single_vector(table'length-1 downto 0);
begin
original_table := table(table'length-1 downto 0);
for i in 0 to original_table'length-1 loop
reversed_table(i) := original_table((original_table'length-1)-i);
end loop;
return reversed_table ;
end reverse_order;

end matrix_class;



library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.matrix_class.all;

entity FIR is
port (

x1 : in logic_4_vector(11 downto 0);
x2 : in logic_4_vector(11 downto 0);
x3 : in logic_4_vector(11 downto 0);
clock1 : in std_logic;
c1 : in std_logic;
c2 : in std_logic;
c3 : in std_logic;
c4 : in std_logic;
c5 : in std_logic;
c6 : in std_logic;
clock2 : in std_logic;
c7 : in std_logic;
c8 : in std_logic;
c9 : in std_logic;
c10 : in std_logic;
c11 : in std_logic;
c12 : in std_logic;
clock3 : in std_logic;
c13 : in std_logic;
c14 : in std_logic;
c15 : in std_logic;
c16 : in std_logic;
c17 : in std_logic;
c18 : in std_logic;
y1 : out std_logic_vector(12 downto 0);
y2 : out std_logic_vector(12 downto 0);
y3 : out std_logic_vector(12 downto 0));
end FIR;

architecture behavioural of FIR is

constant num_of_sub_filter: integer := 2;

signal h1: single_vector(num_of_sub_filter-1 downto 0);
signal h2: single_vector(num_of_sub_filter-1 downto 0);
signal h3: single_vector(num_of_sub_filter-1 downto 0);
signal h4: single_vector(num_of_sub_filter-1 downto 0);
signal h5: single_vector(num_of_sub_filter-1 downto 0);
signal h6: single_vector(num_of_sub_filter-1 downto 0);
signal h7: single_vector(num_of_sub_filter-1 downto 0);
signal h8: single_vector(num_of_sub_filter-1 downto 0);
signal h9: single_vector(num_of_sub_filter-1 downto 0);
signal h10: single_vector(num_of_sub_filter-1 downto 0);
signal h11: single_vector(num_of_sub_filter-1 downto 0);
signal h12: single_vector(num_of_sub_filter-1 downto 0);
signal h13: single_vector(num_of_sub_filter-1 downto 0);
signal h14: single_vector(num_of_sub_filter-1 downto 0);
signal h15: single_vector(num_of_sub_filter-1 downto 0);
signal h16: single_vector(num_of_sub_filter-1 downto 0);
signal h17: single_vector(num_of_sub_filter-1 downto 0);
signal h18: single_vector(num_of_sub_filter-1 downto 0);

begin
process (clock1,c1,c2,c3,c4,c5,c6)

variable fir1 : single;
variable fir_result1: single;
variable h_var1: single_vector(num_of_sub_filter-1 downto 0);
variable coeff_value1: single_vector(num_of_sub_filter-1 downto 0);

-------------************-------------------
variable fir_result2: single;
variable h_var2: single_vector(num_of_sub_filter-1 downto 0);
variable coeff_value2: single_vector(num_of_sub_filter-1 downto 0);

------------**************------------------
variable fir_result3: single;
variable h_var3: single_vector(num_of_sub_filter-1 downto 0);
variable coeff_value3: single_vector(num_of_sub_filter-1 downto 0);

------------*****************---------------

variable fir_result4: single;
variable h_var4: single_vector(num_of_sub_filter-1 downto 0);
variable coeff_value4: single_vector(num_of_sub_filter-1 downto 0);

-------------************-------------------
variable fir_result5: single;
variable h_var5: single_vector(num_of_sub_filter-1 downto 0);
variable coeff_value5: single_vector(num_of_sub_filter-1 downto 0);

------------**************------------------
variable fir_result6: single;
variable h_var6: single_vector(num_of_sub_filter-1 downto 0);
variable coeff_value6: single_vector(num_of_sub_filter-1 downto 0);

------------*****************---------------
variable coefficient_table_var1: single_vector(11 downto 0);
variable y_result1 : signed(12 downto 0);
begin
if rising_edge(clock1) then
for i in 0 to 11 loop
coefficient_table_var1(i) := single(to_integer(unsigned(b1(i))));
end loop;
end if;

if rising_edge(c1) then
for i in 0 to num_of_sub_filter-1 loop
coeff_value1(i) := coefficient_table_var1(i);
end loop;
h_var1 := h1;
h1 <= h_var1;

fir_result1 := sum_of_products (
lower_limit => 0,
upper_limit => num_of_sub_filter-1,
a_in => reverse_order(h_var1),
b_in => reverse_order(coeff_value1));

end if;

if rising_edge(c2) then
for i in 0 to num_of_sub_filter-1 loop
coeff_value2(i) := coefficient_table_var1(i+2);
end loop;
h_var2 := h2;
h2 <= h_var2;

fir_result2 := sum_of_products (
lower_limit => 0,
upper_limit => num_of_sub_filter-1,
a_in => reverse_order(h_var2),
b_in => reverse_order(coeff_value2));

end if;

if rising_edge(c3) then
for i in 0 to num_of_sub_filter-1 loop
coeff_value3(i) := coefficient_table_var1(i+4);
end loop;
h_var3 := h3;
h3 <= h_var3;

fir_result3 := sum_of_products (
lower_limit => 0,
upper_limit => num_of_sub_filter-1,
a_in => reverse_order(h_var3),
b_in => reverse_order(coeff_value3));

end if;
if rising_edge(c4) then
for i in 0 to num_of_sub_filter-1 loop
coeff_value4(i) := coefficient_table_var1(i+6);
end loop;
h_var4 := h4;
h4 <= h_var4;

fir_result4 := sum_of_products (
lower_limit => 0,
upper_limit => num_of_sub_filter-1,
a_in => reverse_order(h_var4),
b_in => reverse_order(coeff_value4));

end if;

if rising_edge(c5) then
for i in 0 to num_of_sub_filter-1 loop
coeff_value5(i) := coefficient_table_var1(i+8);
end loop;
h_var5 := h5;
h5 <= h_var5;

fir_result5 := sum_of_products (
lower_limit => 0,
upper_limit => num_of_sub_filter-1,
a_in => reverse_order(h_var5),
b_in => reverse_order(coeff_value5));

end if;

if rising_edge(c6) then
for i in 0 to num_of_sub_filter-1 loop
coeff_value6(i) := coefficient_table_var1(i+10);
end loop;
h_var6 := h6;
h6 <= h_var6;

fir_result6 := sum_of_products (
lower_limit => 0,
upper_limit => num_of_sub_filter-1,
a_in => reverse_order(h_var6),
b_in => reverse_order(coeff_value6));

fir1 := fir_result1 + fir_result2 + fir_result3 + fir_result4 + fir_result5 + fir_result6;
y_result1 := to_signed(integer(fir1), y_result1'length);
y1 <= std_logic_vector(y_result1);


end if;
end process;

process (clock2,c7,c8,c9,c10,c11,c12)

variable fir2 : single;
variable fir_result7: single;
variable h_var7: single_vector(num_of_sub_filter-1 downto 0);
variable coeff_value7: single_vector(num_of_sub_filter-1 downto 0);

-------------************-------------------
variable fir_result8: single;
variable h_var8: single_vector(num_of_sub_filter-1 downto 0);
variable coeff_value8: single_vector(num_of_sub_filter-1 downto 0);

------------**************------------------
variable fir_result9: single;
variable h_var9: single_vector(num_of_sub_filter-1 downto 0);
variable coeff_value9: single_vector(num_of_sub_filter-1 downto 0);

------------*****************---------------

variable fir_result10: single;
variable h_var10: single_vector(num_of_sub_filter-1 downto 0);
variable coeff_value10: single_vector(num_of_sub_filter-1 downto 0);

-------------************-------------------
variable fir_result11: single;
variable h_var11: single_vector(num_of_sub_filter-1 downto 0);
variable coeff_value11: single_vector(num_of_sub_filter-1 downto 0);

------------**************------------------
variable fir_result12: single;
variable h_var12: single_vector(num_of_sub_filter-1 downto 0);
variable coeff_value12: single_vector(num_of_sub_filter-1 downto 0);

------------*****************---------------
variable coefficient_table_var2: single_vector(11 downto 0);
variable y_result2 : signed(12 downto 0);
begin
if rising_edge(clock2) then
for i in 0 to 11 loop
coefficient_table_var2(i) := single(to_integer(unsigned(b2(i))));
end loop;
end if;

if rising_edge(c7) then
for i in 0 to num_of_sub_filter-1 loop
coeff_value7(i) := coefficient_table_var2(i);
end loop;
h_var7 := h7;
h7 <= h_var7;

fir_result7 := sum_of_products (
lower_limit => 0,
upper_limit => num_of_sub_filter-1,
a_in => reverse_order(h_var7),
b_in => reverse_order(coeff_value7));

end if;

if rising_edge(c8) then
for i in 0 to num_of_sub_filter-1 loop
coeff_value8(i) := coefficient_table_var2(i+2);
end loop;
h_var8 := h8;
h8 <= h_var8;

fir_result8 := sum_of_products (
lower_limit => 0,
upper_limit => num_of_sub_filter-1,
a_in => reverse_order(h_var8),
b_in => reverse_order(coeff_value8));

end if;

if rising_edge(c9) then
for i in 0 to num_of_sub_filter-1 loop
coeff_value9(i) := coefficient_table_var2(i+4);
end loop;
h_var9 := h9;
h9 <= h_var9;

fir_result9 := sum_of_products (
lower_limit => 0,
upper_limit => num_of_sub_filter-1,
a_in => reverse_order(h_var9),
b_in => reverse_order(coeff_value9));

end if;
if rising_edge(c10) then
for i in 0 to num_of_sub_filter-1 loop
coeff_value10(i) := coefficient_table_var2(i+6);
end loop;
h_var10 := h10;
h10 <= h_var10;

fir_result10 := sum_of_products (
lower_limit => 0,
upper_limit => num_of_sub_filter-1,
a_in => reverse_order(h_var10),
b_in => reverse_order(coeff_value10));

end if;

if rising_edge(c11) then
for i in 0 to num_of_sub_filter-1 loop
coeff_value11(i) := coefficient_table_var2(i+8);
end loop;
h_var11 := h11;
h11 <= h_var11;

fir_result11 := sum_of_products (
lower_limit => 0,
upper_limit => num_of_sub_filter-1,
a_in => reverse_order(h_var11),
b_in => reverse_order(coeff_value11));

end if;

if rising_edge(c12) then
for i in 0 to num_of_sub_filter-1 loop
coeff_value12(i) := coefficient_table_var2(i+10);
end loop;
h_var12 := h12;
h12 <= h_var12;

fir_result12 := sum_of_products (
lower_limit => 0,
upper_limit => num_of_sub_filter-1,
a_in => reverse_order(h_var12),
b_in => reverse_order(coeff_value12));

fir2 := fir_result7 + fir_result8 + fir_result9 + fir_result10 + fir_result11 + fir_result12;
y_result2 := to_signed(integer(fir2), y_result2'length);
y2 <= std_logic_vector(y_result2);
end if;
end process;

process (clock3,c13,c14,c15,c16,c17,c18)

variable fir3 : single;
variable fir_result13: single;
variable h_var13: single_vector(num_of_sub_filter-1 downto 0);
variable coeff_value13: single_vector(num_of_sub_filter-1 downto 0);

-------------************-------------------
variable fir_result14: single;
variable h_var14: single_vector(num_of_sub_filter-1 downto 0);
variable coeff_value14: single_vector(num_of_sub_filter-1 downto 0);

------------**************------------------
variable fir_result15: single;
variable h_var15: single_vector(num_of_sub_filter-1 downto 0);
variable coeff_value15: single_vector(num_of_sub_filter-1 downto 0);

------------*****************---------------

variable fir_result16: single;
variable h_var16: single_vector(num_of_sub_filter-1 downto 0);
variable coeff_value16: single_vector(num_of_sub_filter-1 downto 0);

-------------************-------------------
variable fir_result17: single;
variable h_var17: single_vector(num_of_sub_filter-1 downto 0);
variable coeff_value17: single_vector(num_of_sub_filter-1 downto 0);

------------**************------------------
variable fir_result18: single;
variable h_var18: single_vector(num_of_sub_filter-1 downto 0);
variable coeff_value18: single_vector(num_of_sub_filter-1 downto 0);

------------*****************---------------
variable coefficient_table_var3: single_vector(11 downto 0);
variable y_result3 : signed(12 downto 0);
begin
if rising_edge(clock3) then
for i in 0 to 11 loop
coefficient_table_var3(i) := single(to_integer(unsigned(b3(i))));
end loop;
end if;

if rising_edge(c13) then
for i in 0 to num_of_sub_filter-1 loop
coeff_value13(i) := coefficient_table_var3(i);
end loop;
h_var13 := h13;
h13 <= h_var13;

fir_result13 := sum_of_products (
lower_limit => 0,
upper_limit => num_of_sub_filter-1,
a_in => reverse_order(h_var13),
b_in => reverse_order(coeff_value13));

end if;

if rising_edge(c14) then
for i in 0 to num_of_sub_filter-1 loop
coeff_value14(i) := coefficient_table_var3(i+2);
end loop;
h_var14 := h14;
h14 <= h_var14;

fir_result14 := sum_of_products (
lower_limit => 0,
upper_limit => num_of_sub_filter-1,
a_in => reverse_order(h_var14),
b_in => reverse_order(coeff_value14));

end if;

if rising_edge(c15) then
for i in 0 to num_of_sub_filter-1 loop
coeff_value15(i) := coefficient_table_var3(i+4);
end loop;
h_var15 := h15;
h15 <= h_var15;

fir_result15 := sum_of_products (
lower_limit => 0,
upper_limit => num_of_sub_filter-1,
a_in => reverse_order(h_var15),
b_in => reverse_order(coeff_value15));

end if;
if rising_edge(c16) then
for i in 0 to num_of_sub_filter-1 loop
coeff_value16(i) := coefficient_table_var3(i+6);
end loop;
h_var16 := h16;
h16 <= h_var16;

fir_result16 := sum_of_products (
lower_limit => 0,
upper_limit => num_of_sub_filter-1,
a_in => reverse_order(h_var16),
b_in => reverse_order(coeff_value16));

end if;

if rising_edge(c17) then
for i in 0 to num_of_sub_filter-1 loop
coeff_value17(i) := coefficient_table_var3(i+8);
end loop;
h_var17 := h17;
h17 <= h_var17;

fir_result17 := sum_of_products (
lower_limit => 0,
upper_limit => num_of_sub_filter-1,
a_in => reverse_order(h_var17),
b_in => reverse_order(coeff_value17));

end if;

if rising_edge(c18) then
for i in 0 to num_of_sub_filter-1 loop
coeff_value18(i) := coefficient_table_var3(i+10);
end loop;
h_var18 := h18;
h18 <= h_var18;

fir_result18 := sum_of_products (
lower_limit => 0,
upper_limit => num_of_sub_filter-1,
a_in => reverse_order(h_var18),
b_in => reverse_order(coeff_value18));

fir3 := fir_result13 + fir_result14 + fir_result15 + fir_result16 + fir_result17 + fir_result18;
y_result3 := to_signed(integer(fir3), y_result3'length);
y3 <= std_logic_vector(y_result3);
end if;
end process;
end behavioural;




I have got some errors.......


ERROR:HDLCompiler:69 - "F:/vlsi/vlsi.vhd" Line 186: <b1> is not declared.
ERROR:HDLCompiler:622 - "F:/vlsi/vlsi.vhd" Line 186: Near unsigned ; type conversion expression type cannot be determined uniquely
ERROR:HDLCompiler:69 - "F:/vlsi/vlsi.vhd" Line 324: <b2> is not declared.
ERROR:HDLCompiler:622 - "F:/vlsi/vlsi.vhd" Line 324: Near unsigned ; type conversion expression type cannot be determined uniquely
ERROR:HDLCompiler:69 - "F:/vlsi/vlsi.vhd" Line 460: <b3> is not declared.
ERROR:HDLCompiler:622 - "F:/vlsi/vlsi.vhd" Line 460: Near unsigned ; type conversion expression type cannot be determined uniquely
ERROR:HDLCompiler:854 - "F:/vlsi/vlsi.vhd" Line 123: Unit <behavioural> ignored due to previous errors.

please help.....

 

[lucbra]

The compiler is quite clear about the errors, i.e. it should be so difficult (even with basic Xilinx coding) to get rid of the errors.
b1, b2, b3 are not declared, so you will need a structure like signal b1, b2, b3 : std_logic_vector (...)

probably the other errors will disappear after the declaration

BTW: there are other ways to code a FIR filter

 

[demetal]

The compiler is quite clear about the errors, i.e. it should be so difficult (even with basic Xilinx coding) to get rid of the errors.
b1, b2, b3 are not declared, so you will need a structure like signal b1, b2, b3 : std_logic_vector (...)

probably the other errors will disappear after the declaration

BTW: there are other ways to code a FIR filter

i dont know at which line i should insert this command... and can you specify the type of signal i can declare here i.e; STD_LOGIC_VECTOR or other type and also the parameter inside the bracket.....

please help...


thank you.

 

[TrickyDicky]

I suggest you learn the basics of VHDL before attempting to use such a large amount of unsynthesisable VHDL.

What purpose does this code serve if it is not synthesisable?

 

[demetal]

any one please help to simulate this code.....

 

[lucbra]

If I understand you well, you post some code, and the forum should do the simulation for you, debug the whole damn thing, and then post the results?

Sorry sir, like TrickyDicky wrote, learn VHDL, debug it yourself, buy yourself a good simulator, and you will learn about this exercise.

I don't see any benifit in simulating this for you.

 

[demetal]

If I understand you well, you post some code, and the forum should do the simulation for you, debug the whole damn thing, and then post the results?

Sorry sir, like TrickyDicky wrote, learn VHDL, debug it yourself, buy yourself a good simulator, and you will learn about this exercise.

I don't see any benifit in simulating this for you.

hey,
please read the entire forum before posting your comment...
I didnt asked YOU to simulate and send me the result... I have the software and i dont need anyone to simulate it... I have asked help only to remove those error messeges....
If you can... please help...

 

[FvM]

please read the entire forum before posting your comment...
I didnt asked YOU to simulate and send me the result... I have the software and i dont need anyone to simulate it... I have asked help only to remove those error messeges....

I agree, that you strictly spoken didn't ask others to simulate your code. Lucbra did exactly what you asked for, telling where the errors come from. But this wasn't sufficient, apparently, you asked for the exact data type of missing parameters and so on. Answering this question isn't so easy, it requires to analyze the complete code. The effort isn't much different from simulating the code.

The error reveals, that the code can't have ever compiled as is, at least a part has been stripped off. A brief view clarifies, that all numerical quantities are of the type "single", it's definition is missing from the code. Usually it refers to single precission (32 Bit) floating point, but it may have been redefined as real for simulation. The respective library references are also missing, however. These points can be fixed. But who knows, what else is missing to a function code?

 

[vipinlal]

I have written vhdl code for a simple 4 tap fir filter. See if its useful..
VHDL coding tips and tricks: VHDL code for a 4 tap FIR filter

the code is sythesisable too..

 

[snehajose]

Hi,
I saw your code for fir filter in vhdlguru.
H0 <= to_signed(-2,8); why it is declared so?