help on verilog-A VCO

[semitao]

veriloga idtmod

hi
I find a statement in Verilog-A VCO, just as:
phase_nonlin = `M_TWO_PI * vco_gain * idtmod ( V(vin), 0, 1000.0, 0.0);

I don't know why use the function idtmod(), and I cannot understand the meanings about this function in verilogA mannual.
who can help me?

 

[flushrat]

idtmod

phase is integral of frequency modulo 2pi.
vco_gain * V(vin) in your equation is frequency

 

[Teddy]

verilog-a idtmod

https://www.designers-guide.org/Forum/?board=verilogams;action=display;num=1115114515


Circular Integrator Operator
Use the circular integrator operator to convert an expression argument into its indefinitely integrated form.

idtmod(expr [ , ic [ , modulus [, offset [, abstol | nature ] ] ] ] )
expr is the dynamic integrand or expression to be integrated.

ic is a dynamic initial condition. By default, the value of ic is zero.

modulus is a dynamic value at which the output of idtmod is reset. modulus must be a positive value equation. If you do not specify modulus, idtmod behaves like the idt operator and performs no limiting on the output of the integrator.

offset is a dynamic value added to the integration. The default is zero.

The modulus and offset parameters define the bounds of the integral. The output of the idtmod function always remains in the range

offset < idtmod_output < offset+modulus
abstol is a constant explicit absolute tolerance that applies to the input of the idtmod operator. Set abstol at the largest signal level that you consider negligible.

nature is a nature from which the absolute tolerance is to be derived.

The circular integrator operator is subject to the restrictions listed in "Restrictions on Using Analog Operators".

The value returned by the idtmod operator depends on which parameters you specify.

The initial condition forces the DC solution to the system. You must specify the initial condition, ic, unless you are using idtmod in a system with feedback that forces expr to zero. If you use a model in a feedback configuration, you can leave out the initial condition without any unexpected behavior during simulation.

Example
The circular integrator is useful in cases where the integral can get very large, such as in a voltage controlled oscillator (VCO). For example, you might use the following approach to generate arguments in the range [0,2] for the sinusoid.

phase = idtmod(fc + gain*V(IN), 0, 1, 0); //Phase is in range [0,1].V(OUT) <+ sin(2*PI*phase);

 

[semitao]

idtmod verilog-a

thanks,
but I don't know how to choose the modulus?

 

[mike_bihan]

Does hspice support idtmod()?