I think this meets requirments, not yet tested.
C and S each have two pins, one configed as input, the other output, and tied together externally.
Both C & S output pins configed as passive internal pullup so pin can be driven low from external source.
If external logic input is a mechanical switch, easy to add debounce onchip resource to handle
switch bounce.
Clock is set at 1 uS.
When EdgeDetectC detects a rising or falling edge on C it clocks that value into the D which feeds
Sout pin. S changing operates same way on C.
M, its D FF, is cleared if a neg edge detected on C. If a positive edge detected on C then it is set.
Single chip design, no code for this function only, Cypress PSOC 4 or 5LP familiy. Most chip resources
unused, see right hand window used/left.
IDE and Compiler free, board would be ~ $ 10.
Regards, Dana.