allennlowaton
Full Member level 5
Good day guys..
I am doing a DLL right now. I'm having problem regarding the simulation results.
My DLL composed of a phase detector, charge pump and a 5-stage voltage controlled delay element (VCDE).
The simulation results can be shown below:
I can't understand why this DLL acted like an open loop, where in fact I already connected the output of the 5th stage back to the phase detector then to be compared with the reference frequency that leads to the formation of UP signal. The continuous formation of UP signal leads to always charging the charge pump, which can be seen as VCONTROL hugging the VDD.
Help please....
I am doing a DLL right now. I'm having problem regarding the simulation results.
My DLL composed of a phase detector, charge pump and a 5-stage voltage controlled delay element (VCDE).
The simulation results can be shown below:
I can't understand why this DLL acted like an open loop, where in fact I already connected the output of the 5th stage back to the phase detector then to be compared with the reference frequency that leads to the formation of UP signal. The continuous formation of UP signal leads to always charging the charge pump, which can be seen as VCONTROL hugging the VDD.
Help please....