help on a PLL design with pe3236 ,output >8 GHz

[cdlonesome]

note on hybrid pll

how ?
need DDS + PLL ？
need your sugestions ,thanks
8O

 

[guanchoon]

General topology for hybrid DDS+PLL Synthesizer:

[1] DDS is used as the reference clock to the PLL synthesizer. You should be awared of the poor broadband spurious performance of the DDS clcok. Need to take care of the DDS clock leakages, the aliasing products. Advantage: Phase noise of DDS clock gets divided down, and you can change frequency very fast.

[2] for your PLL, because the output is in the 8 GHz region, you probably need some low order frequency mutliplier in your design Suggest to do a 4GHz PLL circuit, followed by a x2 frequency multiplier. You can get a 6GHz PLL IC from Analog Devices. The frequency multiplier can also act as a buffer circuit to isolate the PLL circuit from external circuitry such as transmitter, to avoid external influence on the PLL performance.

Some years ago, Qualcomm has an application note on hybrid DDS+PLL design. You may like to do some research for this topic . 8)

 

[Farhad40]

Hello guanchoon;
Can you upload the app. note to forum? Also what's your opinion about this idea:

producing a widaband synthesizer using a DDS and a frequency multiplier

Have you any experience about this idea?

 

[No one]

Hello Farhad40;
In which frequency range?