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Help on a logic circuit

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ruwan2

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Hi,

I am new to Serdes. I read a paper on line:

https://obrazki.elektroda.pl/8227973900_1395428254.png

https://web.mit.edu/Magic/Public/papers/04586005.pdf

I do not understand Fig.2. The total FIR taps is 5. It uses 4 5-to-1 mux with 1/4 clock. Here I do not understand what controls the 5-to-1 mux. I can understand 1/4 clock, there are 4 FIR tap lines. What is 5 for? It cycles 5 taps coefficients?

Second, it has 11 programmable connections to CMOD. What is 11 for?

Third, I do not understand D.m0' and D.m1'.

Thank you in advance.
 

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