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[SOLVED] HELP NEEDED WITH vsim error (vcom-1134)

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jianhuachews

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Hi guys i was given this error when i tried compiling my program

# ** Error: Lab4B.vhd(40): (vcom-1134) Incompatible modes for port 'agtb_o' in component 'lab4a' when binding to entity 'lab4a'.
# ** Error: Lab4B.vhd(40): (vcom-1134) Incompatible modes for port 'aeqb_o' in component 'lab4a' when binding to entity 'lab4a'.

Does anyone have any idea?

Code:
library IEEE;
use IEEE.std_logic_1164.all;

entity lab4b is port (
		a, b: in std_logic_vector(3 downto 0);
		agtb_o, aeqb_o, altb_o: out std_logic
);

end;

architecture comparator of lab4b is

component lab4a port (a,b: in std_logic;
		agtb_i,aeqb_i: in std_logic;
		agtb_o,aeqb_o: in std_logic
);
end component;

signal agtb, aeqb: std_logic_vector(3downto 0);
signal vdd,vss: std_logic;

begin 
vdd <='1';
vss <='0';

U1: lab4a port map (agtb_i=>vss, aeqb_i=>vdd, a=>a(3), b=>b(3), aeqb_o=>aeqb(3), agtb_o=>agtb(3));
U2: lab4a port map (agtb_i=>agtb(3), aeqb_i=>aeqb(3), a=>a(2), b=>b(2), aeqb_o=>aeqb(2), agtb_o=>agtb(2));
U3: lab4a port map (agtb_i=>agtb(2), aeqb_i=>aeqb(2), a=>a(1), b=>b(1), aeqb_o=>aeqb(1), agtb_o=>agtb(1));
U4: lab4a port map (agtb_i=>agtb(1), aeqb_i=>aeqb(1), a=>a(0), b=>b(0), aeqb_o=>aeqb(0), agtb_o=>agtb(0)); 

agtb_o <= agtb(0);
aeqb_o <= aeqb(0);
altb_o <= not (agtb(0) or aeqb(0));

end;

configuration cc of lab4b is
for comparator 
	for all: lab4a use entity work.lab4a(comparator);
	end for;
end for;
end cc;
 

TrickyDicky

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you've got a component binding to itself. The component does not match the entity declaration.

Your entity is called lab4a, and your component is called lab4a. You're trying to connect something to itself, so you will have infinite recursion, if the component and entity declaration matched.
 
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    sanju_

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jianhuachews

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Hey tricky i know where my mistakes were at.. it camouflaged itself in the component port, i had my declaration mixed up thanks anyway!
 

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