[SOLVED] Help needed"test bench of a counter entering a value in fifo and then reading it out"

[prady019]

Help needed"test bench of a counter entering a value in fifo and then reading it out"

this is code i wrote for test bench in vhdl
tell me did i make any mistake or guide me to write it in more simpler form.
i wrote some on my qures in comments form help me out for that.

**********************************************************
entity counter_data_tb is
end counter_data_tb;

architecture test of counter_data_tb is

component top_level
port ( clk : in std_logic;
rst : in std_logic;
write_request_top : in std_logic;
read_request_top : in std_logic;
fifo_out_top : out std_logic_vector(7 downto 0)
);
end component;

signal clk_test : std_logic := '0';
signal rst_test : std_logic := '0';
signal write_request_top_test : std_logic := '0';
signal read_request_top_test : std_logic := '0';
signal fifo_out_top_test : std_logic_vector(7 downto 0);

constant clk_period : time := 2 ns;
begin

DUT : top_level
port map ( clk => clk_test,
rst => rst_test,
write_request_top => write_request_top_test,
read_request_top => read_request_top_test,
fifo_out_top => fifo_out_top_test
);

clk_genrate : process
begin
clk_test <= '0';
wait for clk_period/2;
clk_test <= '1';
wait for clk_period/2;
end process;

input_genrate : process
begin
wait for 2 ns;
rst_test <= '1';
wait for 2 ns;
rst_test <= '0';
wait for 3 ns;
write_request_top_test <= '1'; -- to make read/write request i thought of this, is this write??
read_request_top_test <= '0';
wait for 2 ns;
write_request_top_test <= '0';
read_request_top_test <= '1';
wait for 2 ns;
write_request_top_test <= '1';
read_request_top_test <= '0';
wait for 2 ns;
write_request_top_test <= '0';
read_request_top_test <= '1';
wait for 2 ns;
write_request_top_test <= '1';
read_request_top_test <= '0';
wait for 2 ns;
write_request_top_test <= '0';
read_request_top_test <= '1';
wait for 2 ns;
write_request_top_test <= '1';
read_request_top_test <= '0';
wait for 2 ns;
write_request_top_test <= '0';
read_request_top_test <= '1';
wait for 2 ns;
write_request_top_test <= '1';
read_request_top_test <= '0';
wait for 2 ns;
write_request_top_test <= '0';
read_request_top_test <= '1';
wait for 2 ns;
write_request_top_test <= '1';
read_request_top_test <= '0';
wait for 2 ns;
write_request_top_test <= '0';
read_request_top_test <= '1';
wait; -- tell me what's this statement doing here??
end process;

end test;

 

[soloktanjung]

Re: Help needed"test bench of a counter entering a value in fifo and then reading it

Try look at this testbench and learn from it: https://www.asic-world.com/code/verilog_tutorial/fifo_tb.v

Thanks.

 

[Er.abdulrehman]

Re: Help needed"test bench of a counter entering a value in fifo and then reading it

Please upload the clear waveform, left most side labels in your waveform is not completely visible,

 

[prady019]

Re: Help needed&quot;test bench of a counter entering a value in fifo and then reading it

They are top level signal's, they are in order as
1. clk
2. rst
3. write_request_top
4. read_request_top
5. fifo_out_top
6. clk_period

- - - Updated - - -

Try look at this testbench and learn from it: https://www.asic-world.com/code/verilog_tutorial/fifo_tb.v


This is an example of Verilog, but m using VHDL.

 

[Er.abdulrehman]

Re: Help needed&quot;test bench of a counter entering a value in fifo and then reading it

What are you writting at 4th clock pulse, and what are you reading at 5th clock pulse.

 

[prady019]

Re: Help needed&quot;test bench of a counter entering a value in fifo and then reading it

i don't know what i did, but my mind is in real mess now.

 

[Er.abdulrehman]

Re: Help needed"test bench of a counter entering a value in fifo and then reading it

First make the counter and then apply to FIFO register