help needed regarding synthesis!

[sudheerprasad]

help regarding synthesis

hi all,
my library doesnt have a d-flip flop clear/preset signals,it only has a dff.
but to synthesize a design i need a flip-flop with clear/preset signals.
if i include a latch in my library can the synthesis tool synthsize a dff with preset/clear signals using the latch

 

[ljxpjpjljx]

Re: help regarding synthesis

no , you need the lib!

 

[amraldo]

Re: help regarding synthesis

I have a question.
Will the synthesizer at this case use whatever is present in the library and add some combinational logic before to the DFF to simulate the preset and clear functionality. I find it logical.
Any comments?
--
Amr Ali

 

[sudheerprasad]

Re: help regarding synthesis

can u send me the layout extracted spice netlist of the the dff with reset if it uses tsmc018,because i need to characterize at different voltages.

 

[D Saurabh]

help regarding synthesis

@amraldo: Yes, the synthesis tool will implement the logic as specified in RTL with whatever cells it has in the library. The tool does not alter the logic/functionality. If you run an equivalence check between the RTL and synthesized netlist, it will and should pass.

 

[amraldo]

help regarding synthesis

Then we can conclude that there is no need for the extra library.
--
Amr Ali

 

[Syswip]

Then we can conclude that there is no need for the extra library.

In this case you should design DFF using nand gates. And during synthesis you should set some timing paths to false.

 

[raju3295]

Then we can conclude that there is no need for the extra library.

In this case you should design DFF using nand gates. And during synthesis you should set some timing paths to false.

Hi can you elaborate on "false pathing"
i hope, synthesiszer will come up with some combo logic to obtain the functionality of s/r and dff,

i think u can dirctly try doing synthesis with what ever the lib cells are avialable.