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help needed: PA affects offset PLL integral phase noise

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carlyou

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To avoid pulling I select offset PLL structure. But at fractional frequency the on-chip PA deteriorates PLL IPN so much, larger power out worse IPN. At integer frequency it's OK. In open loop test the VCO performance doesn't change. If does PA affect N-divider, PFD or CP's linearity? What's the path and mechanism? Thank you.
 

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