Help Needed: Issues on Dummy Layout

[hrkhari]

Hi Guys:

I had laid out a pMOS transistor with grounded dummies poly (gate) as etch guards to reduce mismatch. With reference to the attached figure, I had connected the dummies using metal in a loop surrounding the pMOS transistor. I had read that placing dummy in a continuous ring poly could induce electromagnetic field due to dry etching to produce circulating current that could affect etch rates during the final minutes of etching, hence it is important to employ a gap to interrupt the circulating current. My question is, does this type of connection of dummy(as in the attached figure) would experience the same phenomenon?, Do I have to separate the ground of the dummies to a broken loop connection?. Thanks in advance

Rgds

 

[k_90]

I see no issue with this method of layout. Having a metal ring to conect the poly will reduce the gate capacitance, which is good and speeds up the transistor. Im not sure what Phenomenon your talking about I can only think of antenna errors which wouldnt happen in this case as the metal lines are short, you could run a check on this, Im curious to know why there is only one transistor though, if its a matched device wheres the other one? Even if this issues was true why do you care as it wouldnt effect the working transistor.
I have been a layout enginner since 2000 and have never heard for the issue your dealing with, can you post the link to the documentation?