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SystemVerilog

SystemVerilog

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Help needed in System verilog

dfgt

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module fifito(
input logic clk,
input logic MR, //RESET
input logic [3:0]D, //DATA IN
input logic SO,//read
input logic SI, //write
// input logic TSC,
output logic [3:0]Q, // DATA OUT
output logic DIR,//Empty
output logic DOR //Full
);
logic [15:0][3:0]buffer;
logic [3:0] SO_ptr,SI_ptr;
logic [15:0] estado;

always @ (Q)
begin
assign DIR = (estado == 0);
assign DOR = (estado == {(16){1'b1}});
end


endmodule

  • [Synth 8-27] procedural assign not supported ["C:/Xilinx/Vivado/2022.2/Intento2/Intento2.srcs/sources_1/new/fifito.sv":39]
  • The red part is giving me that error
 
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FvM

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Where got you the idea to use assign inside sequential block? Did you try to simply omit it?
 

dfgt

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Where got you the idea to use assign inside sequential block? Did you try to simply omit it?
I saw a FIFO example here, and once I was trying to synthesize it didn't work.
I took out the "assign", I removed the "always" and "begin" and it works, but now I have another problem. I am using a button to write data, but I think the clock is too fast, since it should be 16 data that I can write, and the 16 data are the same, there is no time to change it. I was trying to use a clock divider, any advice on this?
 

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