Help needed for the design of BGR

[cheenu_2002]

Help needed for BGR

Hi,
I am trying a BGR design (Pls see the attached file ). Initially I am just forcing a constant voltage to both the BJT's which is normally done thru an opamp. I dont know if there is the correct way but I did like that bcoz I dont have a very good opamp design with me as of now (I am doing it as part of study work for my project). I dont know how to check if the BJTs are working properly. The curent in BJT2<39:0> is always in the range of 150a A which is very very less. Could anyone help whats wrong with my learning.

 

[nschutten]

Help needed for BGR

I haven't designed a BGR myself, but looking at your circuit diagram, it does strike me as odd; usually the PFET device sizes are a lot different (e.g. W/L=20/2 or so). And are R0 and R1 meant as a startup circuit? Usually a startup is connected at the gates of the PFETs. And I don't think that the connection between R3 and R4 should be there. I am not sure, but I think that you may want to look into a book such as "ASIC Design in the silicon sandbox" by Keith Barr (I highly recommend this book to anyone starting anyway).

 

[tzg6sa]

Re: Help needed for BGR

Do not short the nodes above the pnps, use an ideal amp instead. There most be one in your standard library.
And remove the resistor divider on the left. Why did you put them there?
The start-up is not a concern since an ideal current source is used for biasing.

 

[cheenu2002]

I have tried the basic BGR topology but I am not able to force same value to both the inputs of opamp. I am not sure if the feedback method I am using is correct.
Can anyone check my schematic and tell me where I am making mistake...
How is the opamp output normally fedback.. I coudnt get any paper which gives that schematic. Almost all of them give only the block diagram where the opamp output is directly connected to the resistors R1, R2 but I dont know how it is done practically.

 

[dick_freebird]

I don't think the output stage is right, it needs to be a replica
of one or the other reference stacks (pick the left hand one,
bjt1 + its resistor). I would expect only about 0.5V output
as-drawn.

If you suspect op amp connection, try swapping the inputs.

Try breaking the loop at the op amp output, run the current
mirror rack with a voltage source, sweep it and watch
the op amp output. If it doesn't look like a great comparator
and you don't see roughly 1/2V at qp5.D and qp5.D at the point
where the output switches, you can look elsewhere for the
topology fault. If it switches the wrong way (in phase
with source voltage) then you only have a polarity problem.

I would go a lot bigger on the FET sizing so as to work
better at low headroom. And I see no explicit startup
circuit, so you might need to run a transient analysis instead
of DC so you can apply some "kick start". or add a DC-functional
startup.