Help needed for the DCM Architecture

[preet]

Dear all,


I am curious to know abt the detailed/ BLOCK Level architecture of XILINX DCM block.
Please help me regarding this as i didn't find any document regarding the same.

Regards

Preet

 

[anjosoviaj]

Hi...

Please look into the chapter on clock management in any of the FPGA/CPLD user guides available in Xilinx. It explains the structure in detail..

Hope u find it...

Regards