wolfrain
Junior Member level 1
- Joined
- Nov 14, 2009
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At this moment I have finished testing my HDL design in simulation and synthesise it in Cadence Encounter RTL Complier. Then I have got the synthesised gate level .v file afterwards, and I simulated it in modelsim.
Also, I walked through a simple place and route in Cadence APR for
created a floorplan
placed the cells
Filled the gaps
Routed the signals
Power and Ground Rings
End Cap Cells
All of these are done automatically by following my supervisor`s notes. At last, I have got the .gds file.
But what is next?
He asked me to extract the detailed timing and power models, also complete timing analysis and power analysis.
What should I do for these?? I really have no idea...
Thank you in advance...I really appreciate for your helps.
regards,
wolfrain
Also, I walked through a simple place and route in Cadence APR for
created a floorplan
placed the cells
Filled the gaps
Routed the signals
Power and Ground Rings
End Cap Cells
All of these are done automatically by following my supervisor`s notes. At last, I have got the .gds file.
But what is next?
He asked me to extract the detailed timing and power models, also complete timing analysis and power analysis.
What should I do for these?? I really have no idea...
Thank you in advance...I really appreciate for your helps.
regards,
wolfrain