cheenu2002
Junior Member level 2
Hi,
I am starting to learn analog IC design with opamp design. I am trying out with a pmos input pair diffamp. The schematic and AC responses are attached with this mail.
My target specs are :
Supply - 1.8 V
Gain - 60 dB
SR - 5 V/us
Load cap - 1 pF
GBW - 5 MHz
Process - 45nm (Cant use L greater than 0.2um)
Vtn - 0.3V ; Vtp - 0.4 V
Kn - 210e-6 ; Kp - 150e-6 where K = UCox
I tried to design with the procedure given in Allen and Hollberg book, but I am getting very absurd device sizes. So, I have just chosen a current of 50uA and made a start. Initally I tried to place all transistors in saturation and then checked the gain and phase. The responses look poor
Need some help to tweak my design. I dont know how experienced designers go about designing opamps. Can anyone help me. Also, one of my basic questions is why the current mirror is not exactly mirroring the current though W/L is same for both the transistors. I couldnt get which parameter is affecting it.
Also, I dont know if this is the correct way to give input and check the specs. I used a 'vdc' source as input with DC = 800mV, AC magnitude = 0.5 and phase of 0 and 180 degrees. Is it correct?
I am starting to learn analog IC design with opamp design. I am trying out with a pmos input pair diffamp. The schematic and AC responses are attached with this mail.
My target specs are :
Supply - 1.8 V
Gain - 60 dB
SR - 5 V/us
Load cap - 1 pF
GBW - 5 MHz
Process - 45nm (Cant use L greater than 0.2um)
Vtn - 0.3V ; Vtp - 0.4 V
Kn - 210e-6 ; Kp - 150e-6 where K = UCox
I tried to design with the procedure given in Allen and Hollberg book, but I am getting very absurd device sizes. So, I have just chosen a current of 50uA and made a start. Initally I tried to place all transistors in saturation and then checked the gain and phase. The responses look poor
Need some help to tweak my design. I dont know how experienced designers go about designing opamps. Can anyone help me. Also, one of my basic questions is why the current mirror is not exactly mirroring the current though W/L is same for both the transistors. I couldnt get which parameter is affecting it.
Also, I dont know if this is the correct way to give input and check the specs. I used a 'vdc' source as input with DC = 800mV, AC magnitude = 0.5 and phase of 0 and 180 degrees. Is it correct?