help! my design toggle rate with VCS 7.0

[wartwo]

ignored cell on vcs

My design run with VCS 7.0 report toggle rate is 0. The cm.log message is following :

Starting toggle coverage for module RM5012_SIM_TOP.RM5012.TOP.RM5012_TOP_ROM
: Starting toggle coverage for module RM5012_SIM_TOP.RM5012.TOP.RM5012_TOP_ROM.u_dafilter_top
: Starting toggle coverage for module RM5012_SIM_TOP.RM5012.TOP.RM5012_TOP_ROM.u_dafilter_top.dainterpolation_inst
: Starting toggle coverage for module RM5012_SIM_TOP.RM5012.TOP.RM5012_TOP_ROM.u_dafilter_top.dainterpolation_inst.udafir
: Module RM5012_SIM_TOP.RM5012.TOP.RM5012_TOP_ROM.u_dafilter_top.dainterpolation_inst.udafir.U4 is ignored. skipping to next module...
: Module RM5012_SIM_TOP.RM5012.TOP.RM5012_TOP_ROM.u_dafilter_top.dainterpolation_inst.udafir.U3 is ignored. skipping to next module...

All the cell is ignored. So the toggle rate is 0.

Please tell me why the cell is ignored.

Note : fsm/cond/line coverage report is not 0. Only toggle rate report is 0.

 

[ljxpjpjljx]

does this cell connected to constant value?

 

[wartwo]

I can't make sure. But this is a way to trace. Thanks a lot.

 

[wartwo]

After simulation, I can make sure the ignored cell's input/output has signal toggled.

Does anyone can help me?

Added after 3 hours 40 minutes:

After simulation, my vcs command is with -cm cond+line+fsm+tgl.

However the output result always report with cond/line/fsm without any tgl information.

Does anyone know the reason ?

 

[wartwo]

The problem finds out.

That is tools's bug.

After update the VCS to newest version.

The problem is solved.