as given initially vout=0 charge on C1 is also zero !! ..
case 1
when sw1 is open terminal 2 is high so output of nor wil be low
case2
when sw1 is closed for some time both terminal 2 and terminal 3 will be at zero voltage n output will be high !!... now charge is developed n when sufficient charge is develop again output will fall to zero
i agree with shiv_emf but i would like to add a point... in case 2 when the input voltage of terminal 3 starts increasing and at a point the output drops to zero and so the capacitor starts discharging through the resistor and hence the output would again become high quickly and this time period depends on the R and C values....
suppose the RC constant is very small then the input at terminal3 might switch before the output switches and this would make the output to switch before it reaches the maximum value and this would lead to a triangle wave......
it would be a triangle since the output cannot switch perfectly i.e.perfect vertical transition...
i dont know influence of second NOR input over the first one , but if it is not interfering , for cmos logic , output voltage should half of power supply and logic ic should work in linear mode if button pressed for time more than multiple of R*C value .
i agree with shiv_emf but i would like to add a point... in case 2 when the input voltage of terminal 3 starts increasing and at a point the output drops to zero and so the capacitor starts discharging through the resistor and hence the output would again become high quickly and this time period depends on the R and C values....
This circuit might not work for a TTL gate ... as one of the NOR gate inputs is connected to the ground through the capacitor... In TTL logic logic zero is only when the input is connected to the ground and not when the input is floating... so one of the inputs of the logic gate connected through the capacitor will be in logic 1 making the output to remain zero always...
i dont know influence of second NOR input over the first one , but if it is not interfering , for cmos logic , output voltage should half of power supply and logic ic should work in linear mode if button pressed for time more than multiple of R*C value .
that notation is actually to indicate that the structure of the electrode inside a capacitor is changed for the sake of increasing the capacitance.....
but when used in the reverse direction only a small decrease in the capacitance and voltage rating results....
This is a gated oscillator. With the switch open, it is stopped. Once the switch is closed, the output goes high, charging the capacitor. Once the logic one level is reached at the capacitor, the output goes low and the capacitor discharges through the resistor to the output. For reliable operation, schmit trigger inputs are preferred. The period of oscillation starts after an initial delay produces a square wave output. The gate is not biased into linear operation.
how do you say the feedback is negative.... check out the sign of the output and the sign of the change in voltage across capacitor i.e feedback.... the output aids the input.... so it is positive feedback only.....