Help me with synthetic coding style in Verilog

[zhangpengyu]

help for verilog

Hi
guys!

always @( a )
b <= a;

Is this synthetic coding style?
If so,what will the code be synthesized to ?


Thanks!


zhpy

 

[jelydonut]

Re: help for verilog

that will synthesize to a wire...

a--b

the equlivilant statement would be

assign b = a;

jelydonut

 

[z81203]

help for verilog

yeah,

--
wire a, b;
assign b = a;
--

 

[kelvin_sg]

Re: help for verilog

Yes, it is synthisizable code. It is equivalent to assign statement and
there is nothing wrong with that style.

When the design gets complicated, for example, when there are tens
of variables in the sensitivity list, an always @ () statement saves the
day.

Both methods are acceptable and correct coding style. 8)

Kelvin