fredrichodie
Newbie level 3
It is receiving data from a gyroscope, the format is a synchronized signal, when the gyro-clock has pulses the data is valid. A whole frame is 32 bits. then the clock goes zero for a little period.
The data is saved to a vector and it's sending the data through RS232 format to a computer.
The question is that it should only send after receiving a 32 bit. I use the state machine. I wanna make it as simple as I can so I only define 2 states: receive and send.
But the simulation seems the state never jumped from the receive state to send state. I am alone on this now and can't find a way to solve it T_T...
I'm a VHDL starter so my coding style might seems ridiculously immature...
here's my code:
entity Main is
port (gyroclk : in std_logic;
gyrodata : in std_logic;
seclk : in std_logic;
serial: out std_logic
);
end Main;
architecture Behavioral of Main is
type iState is (send, receive);
signal Cache: std_logic_vector ( 0 to 54 ):="0100000001100000000011000000000110000000001100000000011";
signal n: integer range 0 to 31:=0;
signal i: integer range 0 to 54:=0;
signal state: iState;
begin
state_control
rocess(seclk, gyroclk, n, i)
begin
if i=0 then
state<=RECEIVE;
end if;
case state is
when RECEIVE =>
if (n=31) then
state<=SEND;
end if;
when SEND =>
if (i=54) then
state<=RECEIVE;
end if;
when others => null;
end case;
end process;
receive_gyro
rocess(gyroclk)
begin
if state=RECEIVE then
if gyroclk'event and gyroclk='1' then
if n>=0 and n<7 then
Cache(n+2)<=gyrodata;
elsif n>=7 and n<14 then
Cache(n+6)<=gyrodata;
elsif n>=14 and n<21 then
Cache(n+10)<=gyrodata;
elsif n>=21 and n<28 then
Cache(n+14)<=gyrodata;
elsif n>=28 and n<32 then
Cache(n+18)<=gyrodata;
end if;
if n<31 then
n<=n+1;
elsif n=31 then
n<=0;
end if;
end if;
end if;
end process;
send_RS232
rocess(seclk)
begin
if state=SEND then
if seclk'event and seclk='1' then
serial<=Cache(i);
if i <54 then
i<=i+1;
elsif i=54 then
i<=0;
end if;
end if;
elsif state=RECEIVE then
serial<='1';
end if;
end process;
end Behavioral;
The data is saved to a vector and it's sending the data through RS232 format to a computer.
The question is that it should only send after receiving a 32 bit. I use the state machine. I wanna make it as simple as I can so I only define 2 states: receive and send.
But the simulation seems the state never jumped from the receive state to send state. I am alone on this now and can't find a way to solve it T_T...
I'm a VHDL starter so my coding style might seems ridiculously immature...
here's my code:
entity Main is
port (gyroclk : in std_logic;
gyrodata : in std_logic;
seclk : in std_logic;
serial: out std_logic
);
end Main;
architecture Behavioral of Main is
type iState is (send, receive);
signal Cache: std_logic_vector ( 0 to 54 ):="0100000001100000000011000000000110000000001100000000011";
signal n: integer range 0 to 31:=0;
signal i: integer range 0 to 54:=0;
signal state: iState;
begin
state_control
begin
if i=0 then
state<=RECEIVE;
end if;
case state is
when RECEIVE =>
if (n=31) then
state<=SEND;
end if;
when SEND =>
if (i=54) then
state<=RECEIVE;
end if;
when others => null;
end case;
end process;
receive_gyro
begin
if state=RECEIVE then
if gyroclk'event and gyroclk='1' then
if n>=0 and n<7 then
Cache(n+2)<=gyrodata;
elsif n>=7 and n<14 then
Cache(n+6)<=gyrodata;
elsif n>=14 and n<21 then
Cache(n+10)<=gyrodata;
elsif n>=21 and n<28 then
Cache(n+14)<=gyrodata;
elsif n>=28 and n<32 then
Cache(n+18)<=gyrodata;
end if;
if n<31 then
n<=n+1;
elsif n=31 then
n<=0;
end if;
end if;
end if;
end process;
send_RS232
begin
if state=SEND then
if seclk'event and seclk='1' then
serial<=Cache(i);
if i <54 then
i<=i+1;
elsif i=54 then
i<=0;
end if;
end if;
elsif state=RECEIVE then
serial<='1';
end if;
end process;
end Behavioral;
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