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Help me with my code (formality issues)

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varkylin

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About the formality

hi all
we have a block, the code is:
-----------------------------------------------------------------
module top(..);
input mem_out;
.
.
.
float_mem float_mem(
.mclk(mclk),
.mem_out(mem_out),
.
.
);

endmodule

module float_mem();

output mem_out;

endmodule
---------------------------------------------------------------------
and we make a mistake. the signal mem_out is the output signal of
the float_mem,but in the top module,the signal is as input signal.
and we synthesize,the error was not found. similarily, do formality.
the HDL code match with the synthesized code.
Now, i have a question, if we can find the problem when do formality.
and how to configure the tool of formality.
thank you very much
 

About the formality

Does anybody know ? plz give me the advice . 3x
 

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