balou3
Newbie level 3
mixed-signal simulation
Hello people,
I hope that someone can give me some ideas concerning mixed-signal simulation. I have to simulate a memory built in Virtouso (Cadence), the cells and sense amplifiers, decoder are analog, input/output stages are digital. Additionally, I have a finctional unit written in Verilog. I have to run different test patterns to define fault coverage of them. First time I used SpectreVerilog, but it's quite slow, so I need another way to simulate. Does someone know???? :?:
Hello people,
I hope that someone can give me some ideas concerning mixed-signal simulation. I have to simulate a memory built in Virtouso (Cadence), the cells and sense amplifiers, decoder are analog, input/output stages are digital. Additionally, I have a finctional unit written in Verilog. I have to run different test patterns to define fault coverage of them. First time I used SpectreVerilog, but it's quite slow, so I need another way to simulate. Does someone know???? :?:
