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Help me with mixed-signal simulation!

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balou3

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mixed-signal simulation

Hello people,

I hope that someone can give me some ideas concerning mixed-signal simulation. I have to simulate a memory built in Virtouso (Cadence), the cells and sense amplifiers, decoder are analog, input/output stages are digital. Additionally, I have a finctional unit written in Verilog. I have to run different test patterns to define fault coverage of them. First time I used SpectreVerilog, but it's quite slow, so I need another way to simulate. Does someone know???? :?:
 

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wang1

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Re: mixed-signal simulation

You can try hs1m or nan0sim. :)
 

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