Lance1314
Newbie level 1
Figure 1 shows a simple block diagram of an up-down synchronous counter. When the switch is ON, the counter will count in the sequence given ( 11, 12, 13, 14, 15 ). The sequence is to be displayed on two seven-segment displays. When the reset button is pressed, the counter will reset to 00. When the switch is OFF, the counter will count in the reverse sequence.
1. Design a logic circuit that meets the design specifications above.
2. The logic circuit includes 2 seven-segment decoders.
Anyone please show me your design steps. Thanks a lot for your help.
1. Design a logic circuit that meets the design specifications above.
2. The logic circuit includes 2 seven-segment decoders.
Anyone please show me your design steps. Thanks a lot for your help.