Help me with designing fifo

[somayeh]

design fifo

Hello,
I should design it with "DXP" microsoft . I should use TSK51A or TSK51 for building fifo with the microsoft.
please help me.[/code]

 

[kangta]

Re: design fifo

what the concrete project do u want .
I have VHDL code for fifo . I hope it can help u !
-- A First-in First-out Memory
-- a first-in first out memory, uses a synchronising clock
-- generics allow fifos of different sizes to be instantiated
-- download from: www.fpga.com.cn & www.pld.com.cn

library IEEE;
use IEEE.Std_logic_1164.all;

entity FIFOMXN is
generic(m, n : Positive := 8); --m is fifo depth, n is fifo width
port(RESET, WRREQ, RDREQ, CLOCK : in Std_logic;
DATAIN : in Std_logic_vector((n-1) downto 0);
DATAOUT : out Std_logic_vector((n-1) downto 0);
FULL, EMPTY : inout Std_logic);
end FIFOMXN;

architecture V2 of FIFOMXN is

type Fifo_array is array(0 to (m-1)) of Bit_vector((n-1) downto 0);
signal Fifo_memory : Fifo_array;
signal Wraddr, Rdaddr, Offset : Natural range 0 to (m-1);
signal Rdpulse, Wrpulse, Q1, Q2, Q3, Q4 : Std_logic;
signal Databuffer : Bit_vector((n-1) downto 0);

begin

--pulse synchronisers for WRREQ and RDREQ
--modified for Synplify to a process

sync_ffs : process
begin
wait until rising_edge(CLOCK);
Q1 <= WRREQ;
Q2 <= Q1;
Q3 <= RDREQ;
Q4 <= Q3;
end process;

--concurrent logic to generate pulses

Wrpulse <= Q2 and not(Q1);
Rdpulse <= Q4 and not(Q3);


Fifo_read : process
begin
wait until rising_edge(CLOCK);
if RESET = '1' then
Rdaddr <= 0;
Databuffer <= (others => '0');
elsif (Rdpulse = '1' and EMPTY = '0') then
Databuffer <= Fifo_memory(Rdaddr);
Rdaddr <= (Rdaddr + 1) mod m;
end if;
end process;


Fifo_write : process
begin
wait until rising_edge(CLOCK);
if RESET = '1' then
Wraddr <= 0;
elsif (Wrpulse = '1' and FULL = '0') then
Fifo_memory(Wraddr) <= To_Bitvector(DATAIN);
Wraddr <= (Wraddr + 1) mod m;
end if;
end process;

Offset <= (Wraddr - Rdaddr) when (Wraddr > Rdaddr)
else (m - (Rdaddr - Wraddr)) when (Rdaddr > Wraddr)
else 0;

EMPTY <= '1' when (Offset = 0) else '0';
FULL <= '1' when (Offset = (m-1)) else '0';

DATAOUT <= To_Stdlogicvector(Databuffer) when RDREQ = '0'
else (others => 'Z');

end V2;

 

[go4sandesh_vsn]

Re: design fifo

hi can u plz tell me where to get details abt the FULL Implementation Of ASYNCHRONOUS FIFO........(paper design as well)

 

[altair_06]

Re: design fifo

Check this link:
http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO2.pdf

 

[sheik_vb]

Re: design fifo

Check the following link........


https://www.xilinx.com/ipcenter/catalog/logicore/docs/async_fifo.pdf

 

[go4sandesh_vsn]

Re: design fifo

thnx buddy....it was of gr8 help

can u tell me if we can use Grey Counter followed by grey to binary conveter n then use this binary count to compare between the two binary pointers (write_bin_ptr and read_bin_ptr) .
the grey counter pointer (write_grey_ptr and read_grey_ptr) are just used for synchronisation and after synchronising they are converted to binary . Then they r compared with the other binary_ptr.

 

[Iouri]

design fifo

Why does someone needs to design FIFO??? All vendors now have free IP of FIFO in there tools.
Designing FIFO it is not something simple due to the fact read and write operation can be going at the same time at the same locatio, clock difference, pipeling and etc...

Can someone explain....

Thanks

 

[go4sandesh_vsn]

Re: design fifo

ya hi..........i needed that.......coz i m a student n not a professional........at present we r analyzing problems like async FIFO design, 16 bit RISC processor design n lotz more.......thats y i asked........by the way got a lot of stuff from those links...
thnx