Continue to Site

# Help me with designing a LDO regulator

Status
Not open for further replies.

#### jutek

##### Full Member level 4
some LDO questions

hello

i'm designing the LDO regulator, but i am a beginier and have some problems and questions.

i've read a article by TI and author wrote that PMOS-pass device has 8V/V gain. it's an example, but i wonder how to set pass device gain.
the overall open-loop gain is Gopa*Gpmos*Gfeed(which is negative)

i am simulating the ldo, but didn't notice pass device gain. it's rather suppression.

and what about pmos size, how large it should be?

what is the range of opamp typical DC gain

what load-current raising-falling time i should use during transient simulation?

regards

#### jwfan

##### Member level 4
Re: some LDO questions

The Pmos is a CS amplifier if it is in saturation region. So, it has gain = gm*Rload.
The size of the PMOS is determined by your maximum output current.
The DC gain of the OpAmp is determined by you loop stability and the output accuracy.
The application of your LDO determined the rise and fall time of the LDO load current.

### jutek

Points: 2

#### v_c

##### Advanced Member level 2
Re: some LDO questions

Are you looking at the article "Stability Analysis of low-dropout linear regualators with a PMOS pass element" by E. Rogers?

$G_{pmos} = g_m R_{o,pmos}$

where $g_m$ is the transconductance of the FET. I believe $R_{o,pmos}$ is given as $65 \Omega$, so I think that would make $g_m=0.123 A/V$. I think you can use the transconductance in a spice model. Note that in this system the PMOS is integrated into the IC so there is no way to know all of the parameters.

Also note that in this paper he assumes that the output load resistance is high -- high enough to be neglected from the expressions from the poles and zeros that are calculated.

For more information, please take a look at the paper "Understanding the stable range of equivalent series resistance of an LDO regulator"
by Bang S. Lee. https://focus.ti.com/lit/an/slyt187/slyt187.pdf
Here they refer to the transconductance as $g_p$
The information here is used in the paper by Rogers.

Best regards,
v_c

Last edited by a moderator:

### jutek

Points: 2

#### jutek

##### Full Member level 4
Re: some LDO questions

jwfan said:
The Pmos is a CS amplifier if it is in saturation region.
how to assure the PMOS is in saturation region. I should set opamp output to ranges which fully off and on the pass device, right?

jwfan said:
The DC gain of the OpAmp is determined by you loop stability and the output accuracy.

yes, i've noticed it. but how far should i go with opamp's gain to ensure low quiescent current work. it's the main tradeoff. i need rough values. i'm modelling it and then i'll have to design low voltage opamp with this gain.

Added after 29 minutes:

v_c said:
Are you looking at the article "Stability Analysis of low-dropout linear regualators with a PMOS pass element" by E. Rogers?

$G_{pmos} = g_m R_{o,pmos}$

i've looked to output file and have gm=35.35m and Rout(at the output of LDO) only 0.5ohm - i've got it from .tf analysis am i right??
You wrote Ro,pmos so is that 1/gds?? if yes gds is equal to 1.92, W/L is 10k
what's wrong, maybe my model is not correct. Did you hear about any applications modelling it?

v_c said:
I think you can use the transconductance in a spice model.
so i should use constant gm value instead of real PMOS during the simulation?
if yes so what value. i thought to model gm during saturation region to change with current

v_c said:
Also note that in this paper he assumes that the output load resistance is high -- high enough to be neglected from the expressions from the poles and zeros that are calculated.

why neglected?? if it's high, the pole layis in low frequency (see example in this paper fp3=2.65k)

i don't understand also one thing. I think the bypass capacity is not necessary, and i would consider only two low freq poles and one zero.
but if i use buffer at the opamp's output its output impedance will be low, and will create high frequency pole.
so it will last only one low frequency pole and the zero won't be essential

correct me if i'm wrong, please

regards

Luke

Last edited by a moderator:

#### jwfan

##### Member level 4
Re: some LDO questions

When you input and output range is known, make sure the output of the error amplifier satify Vcs > Vgs - Vth

Status
Not open for further replies.