Help me with designing a 8 bit binary comparator using VHDL

[sssr]

Comparator

Hi

I have to design a 8 bit binary comparator using VHDL that consists of 3 inputs -
two data words (8 bit vector) and an input state (2 bit vector). There are two outputs - output state (2 bit vector- '00' => A=B, '01' => A>B etc ) and a Bitwise Exclusive-OR of the input words (8 bit vector). The design can only use 1 and 2 input nand gates.

I'm having a bit of trouble getting started with the design. I don't know what input state does. Can anyone help or point me in right direction.

Thanks

 

[salma ali bakr]

Re: Comparator

can u please explain more the design required cause it is somehow not obvious (to me at least)....it is easy don't worry...but i am just a bit confused about the specs

thanks,
Salma

 

[sssr]

Re: Comparator

thanks for the reply

First I have to design an 8-bit module comparing the two input vectors. Then I have to
use two of the modules to design a 16-bit binary comparator. That is pretty much all the information I've been given.

 

[salma ali bakr]

Re: Comparator

chk out this link:

http://esd.cs.ucr.edu/labs/tutorial/

hope it is useful

Salma

 

[master.ro]

Re: Comparator

I think that at the input state you have to connect the output state of another comparator.
When you'll design the 16 bits comparator you'll need to tell to the comparator of the least significant 8 bits the result of the comparison of most signifiant 8 bits.

 

[sssr]

Re: Comparator

thanks for your help - should be able to figure it out now