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Help me with Chip Implement flow from RTL to GDSII

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zackwang

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Chip Implement flow

EDA tools is very complex.

Anybody have good idea for Chip Implement flow from RTL to GDSII.

I use synopsys flow

DC=>PC=>astro (primtime)
 

philewar

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Well, you still lack simulation tools and layout tools.

For Very DSM process, power, si and formal verification tools are needed.
 

sigurdwang

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Re: Chip Implement flow

You could reference the book, "ADVANCED ASIC CHIP SYNTHESIS" by Himanshu Bhatnagar, 2nd Edition.
 

bluep

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In fact, Synopsys has a serial of EDA tools to design a chip from RTL to GDSII. But the layout tool of Candence (SE) is better than Synopsys's.
 

philewar

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bluep said:
In fact, Synopsys has a serial of EDA tools to design a chip from RTL to GDSII. But the layout tool of Candence (SE) is better than Synopsys's.

Astro is also competitive when compared to SE.
 

nozone

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How about M@gm@, is it too simple compared with the above ones?
 

cdic

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Re: Chip Implement flow

without good library, magma can do nothing.
 

linuxluo

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Re: Chip Implement flow

hi, bluep
I think what you mean is that the best floorplan tools is cadence firstencounter(fe) .
and now m@gm@ is also simple to master and can produce better result.
 

armer

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Re: Chip Implement flow

Astro is not better than SE, there are so many bugs in it. I thing SOC encounter is strong.
But Astro is cheap than SE, so many company use astro.
 

gerryhsu

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Re: Chip Implement flow

armer said:
Astro is not better than SE, there are so many bugs in it. I thing SOC encounter is strong.
But Astro is cheap than SE, so many company use astro.

No, it's not cheap ! People sometime are not reasonable in choosing for their flow. Mostly influenced by their past experience and the convenience of the same vendor suite of design flow.
Magma is good but it basically still be considered a point tool. It requires some more time to ally with other big guy to make a good suite.
 

linuxluo

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Re: Chip Implement flow

hi, all
I think in the p&r tools, now astro and socencounter is just the same capacitance, but socencounter include firstencounter that is the best in floorplan tools. so someone think socencounter is the best p&r, but if we input the reulst from fe to astro or socencounter, we can get the nearly same p&r result.
 

my_design

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It is well known that Synopsys has famous synthesize tool, and Candence has famous layout tool.
 

cdic

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Re: Chip Implement flow

cdic said:
without good library, magma can do nothing.

With good library, M@gm@ can do "everything"
in my case, After 2weeks struggling with the d@mn library, M@gm@ reduced the chip size by 20%, Passed formal check. in terms of timing, M@gm@ beat PC,@stro & S0CEncounter +PK$. I am pretty sure it will close timing for this 400MHz, 180KInst. aggressive RISC cpu design in another 2weeks.
 

joe2moon

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Re: Chip Implement flow

>>> With good library, M@gm@ can do "everything"

Can not Magma support Synopsys' .lib fomat ?

Why the salesman say it's able to do this 8O
==============================================
Today, many EDA tool vendors have provided their own RTL-to-GDSII flow:

Synopsys: DC + PC + ApolloII (or Astro)
Cadence: BuildGate + FE + SoC-Encounter
Mentor: ???
Magma: Blast RTL + Blast Fusion

But all of them are "implementation" tool !

You still need some "analysis", .i.e. sign-off tool to verify your job.
==============================================

By the way, it seems that you can gain a shorter turn-around time through Magma's flow.
 

cdic

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Re: Chip Implement flow

1. m@gm@ support syn0psys .lib.
2. you do gain much in terms of turn around time/timing closure with m@gm@, if you have ENOUGH license.
3. Implementation & verification are different field. RTL2GDS means implementation. actually only one company can cover whole ic design, that is the reason it's stock can go up to $60 then split, and now it's above 30.
4. m@gm@ is kind of buggy, especially for linux platform.
 

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