Help me with ATPG && test pattern simulation

[kenanou]

atpg netlist

Hi everybody,
I generated a test pattern using Encounter test, the global fault coverage is nearly 98%, but the simulation results says there are 2407243 good comparing vectors and 259 miscomparing vectors . the simulation tool I used is Nc-verilog .

I have already added the two parameters "-NOTimingChecks -Delay_mode unit". Could anybody help me? Thanks!

santhosh007 could you help me again?

 

[santhosh007]

parallel and serial pattens atpg

definitely i can help you. Is it a stuck@ patterns?. parallel or serial?. is that shift simulation is passed or not?. can you share me the failure log?.

 

[kiranks9]

First check the scan chain pattern is passing or not? if it pass, then check which pattern is failing. Before that check properly all u r library cellls proper ot not? it is very important. Do paarallel simulation, check which flop is failing, transcript will give clear picture where it is exactly failing

 

[ljxpjpjljx]

maybe some condition you not set properly!

 

[kenanou]

the miscomparing vector is in the logci scan procedure, the shift simulation has passed.

the Sim1 is the miscompare log and the waveform which I think is not correct,
the output pin Q should be 1'b0 when the clock pin CK is high,



as a result , I added a delay cell before the CK pin, the simulation results seams ok now. The following is the comparation of the netlist before and after manully modified.



I am not sure whether that is correct, or what simulation codition should I add, thanks!

I use the serial test pattern , and deleted the other signal pins except those used in scan test, if not, the simulation will report expext 'Z' but simulated '1'/'0' on those analog voltage pad. Thanks!

 

[sunilbudumuru]

Hello Friend,

R u sure you are reading the updated SDF file while doing the simulations.

If you are working on Postlayout netlist, do the STA and get the updated SDF file from it. And then do the simulations together with the SDF file. You no need to manually add buffers in the clock path.

If you are doing so, verify the Library simulation model if it verifies the negative hold checks.

Sunil Budumuru

 

[kenanou]

Hello Friend,

R u sure you are reading the updated SDF file while doing the simulations.

If you are working on Postlayout netlist, do the STA and get the updated SDF file from it. And then do the simulations together with the SDF file. You no need to manually add buffers in the clock path.

If you are doing so, verify the Library simulation model if it verifies the negative hold checks.

Sunil Budumuru

Thanks, I am working on Post-Layout netlist.
I used the SOC Encounter to do timing closure, and write out an sdf file, Will this SDF file be ok?

My doubt is that when I doing the ATPG, I only input the post layout netlist and the verilog std. cell models , the Encounter test (ATPG tool) will analysis the delay based on the verilog model files, but in fact , the delay should include those time on the wires, So how does ATPG tools solving this problem when working on the Post Layout netlist. Thanks !

 

[dporeddy]

To get more answers for your ATPG question please check the forum www.rtl2gates.com. The moderators of this forum are DFT engineers.

 

[sunilbudumuru]

Hello friend,

for ATPG post layout simulations to pass, you need to read the SDF file together with the library models. else simulations will fail. Be sure that your LIB model have negative hold checking capability in it.

Hope this will helps you.

By the way, I've used SDF file from PT n never used the SDF file from SOCE. I cannot comment on that.

Regards,
Sunil Budumuru

For more information..
www.asic-dft.com