Help me with " a APB writing register process "

[microe_victor]

Help me this typical APB writing process
which is described like the pic below

please use verilog to write this, thank you

PS:
Here is my code , i did not implement all the function. It is my first time to write RTL code, so I think there might be some misunderstanding to the APB protocol




always @(posedge PCLK)
begin
if(PRESET)
begin
state <= INI;
tag_addr <= 0;
data <= 32'b0;
end
else
begin
case(state)
INI :
begin
if((PSELE==1'b1) && (PENABLE == 1'b0))
state <= SELECT;
else
state <= INI;
end
SELECT :
begin
if((PSELE==1'b1) && (PENABLE==1'b1))
begin
state <= ENABLE;
if(addr == ADDRESS )
tag_addr <= 1'b1;
else
tag_addr <= 1'b0;
end
else
begin
state <= INI;
end
end
ENABLE:
begin
if(tag_addr)
data <= PDATA;
else
data <= data;
if((PSELE==1'b1) && (PENABLE==1'b0))
state <= SELECT;
else
state <= INI;
end
default :
state <= INI;
endcase
end
end

 

[aji_vlsi]

Re: Help me with " a APB writing register process &quot

Sorry this post does not directly solve your problem via some code. But rather the concept/idea/process as used in industry. WHat you are looking for is "verification" - once you believe you have coded some thing, you need to "verify" it really does what you intended to. There are several techniques for this, but the core is to develop a testbench of some sort for this. Take a look at my course that I offer in this domain: Comprehensive Functional Verification, see: www.noveldv.com

As some pointers, there are tools that can generate some testvectors once you give the timing diagram, IIRC - TImingDesigner, TestbenchPro (www.synapticad.com) etc. But nothing beats a well designed testbench!

HTH
Ajeetha, CVC
www.noveldv.com