Ganesan_R
Junior Member level 1
Dear Sir,
I am getting doubt whether Vivado 2015.2 simulator supports passing matrix as input arguments in a task.
Here is the main design code:
Here is the test bench code:
The program outputs as
I am also attaching the screen shot.
Thanks.
Yours sincerely,
R. Ganesan.
I am getting doubt whether Vivado 2015.2 simulator supports passing matrix as input arguments in a task.
Here is the main design code:
Code Verilog - [expand] 1 2 3 4 `timescale 1ns / 1ps module NoC_RG_demux_matrix_input(input wire clk,input wire [7:0] o1); endmodule
Here is the test bench code:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 `timescale 1ns / 1ps module tb_NoC_RG_demux_matrix_input(); reg [7:0] o1; reg [7:0] NoC_temp_data; reg clk; NoC_RG_demux_matrix_input N1(.clk(clk),.o1(o1)); initial begin clk=0; @ (posedge clk) begin NoC_Commu_pop({0,1},NoC_temp_data); NoC_Commu_pop({1,4},NoC_temp_data); end end always #5 clk= ~clk; always @ (NoC_temp_data) begin o1=NoC_temp_data; $monitor("output o1= %d",o1); end task NoC_Commu_pop; input wire [7:0] source[0:1]; output reg [7:0] NoC_temp_data; begin $monitor("source[0]= %d",source[0]); $monitor("source[1]= %d",source[1]); @ (posedge clk) begin if ({source[0],source[1]}=={4,1}) NoC_temp_data=8; else NoC_temp_data=4; end end endtask; endmodule
The program outputs as
I am not getting why source[0] =0 source[1]=1 ;source[0]=1 source[1]=4 which is not happening? Why?source[0]=0
source[1]=1
source[1]=4
output o1=4
I am also attaching the screen shot.
Thanks.
Yours sincerely,
R. Ganesan.
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