buenos
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1. sometimes the dram vendors, processor vendors specify the AC timing parameters with different names.
2. The Jedec specified lots of timing parameters, (about 30). is there a good paper where someone explains ALL of them? Not just a sentence, but full explanation. The papers what I found, they describe a few. 10% max. I have no idea about what do the rest mean.
3. The timing calculations are done in a totally different way on application notes from different companies. they use and miss different parameter-sets. (I checked: Micron, AMD, Freescale papers). Some of them use some jedec parameters, but not the others... I have a feeling that all of them have at least 60% error, so they dont make any sense.
how to find the way in this jungle?
(I was talking about mostly byte-lane timing, not the cas latencies and similar things...)
2. The Jedec specified lots of timing parameters, (about 30). is there a good paper where someone explains ALL of them? Not just a sentence, but full explanation. The papers what I found, they describe a few. 10% max. I have no idea about what do the rest mean.
3. The timing calculations are done in a totally different way on application notes from different companies. they use and miss different parameter-sets. (I checked: Micron, AMD, Freescale papers). Some of them use some jedec parameters, but not the others... I have a feeling that all of them have at least 60% error, so they dont make any sense.
how to find the way in this jungle?
(I was talking about mostly byte-lane timing, not the cas latencies and similar things...)