Help me to understand Fully Differential Switched Capacitor

[snoop835]

Hi all,

I am currently need to understand the principle operation of fully differential switched capacitor comparator. The schematic and timing diagram are attached in pdf format.

let me quote the paragraph explaining the principle operation of the circuit.

'The sub-ADC in each pipeline stage consist of two fully diferential comparator shown in pdf attachment. In the 1.5 bit per stage architecture, the sub-ADC threshold are +Vref/4 and -Vref/4, where the ADC input range is -Vref to +Vref differential. The switched capacitor comparator operates on two phase non-overlapping clock. The differencing network samples Vref during phase Q2 onto capacitor C, while the input at capacitor 3C is shorted giving differential zero. During phase Q1, the input signal Vi is applied at the input of both capacitors, causing a differential voltage proportional to Vi - Vref/4 to appear at the
input of the comparator preamp. At the end of phase Q1 (Q1bar high) the regenerative
flip-flop is latched to make the comparison and produce digital levels at the
output Vo.During phase Q1, the input signal Vi is applied at the input of both capacitor

My problem is I don't fully understand the circuit operations. I want to understand the mathematics behind this operation. How to we get the threshold +vref/4 and
-Vref/4?

Pls help me on this.

thanks in advance

 

[blueant]

too difficult for me ^-^

 

[Btrend]

Re: Help me to understand Fully Differential Switched Capaci

at the end of Φ2, Qc1=Vrefp*C, Qc2=0*C, where C1=C, C2=3C
at the start of Φ1, Vc1(Φ2end)=Vc2(Φ2end)==Qc1/(C1+C2)=Vrefp/4
at the end of Φ1, left plate of C1 is at Vip, but there is no path for the charge to leak (assume high impedance), so the charge should contain in the same place as the end of Φ2.
cause Vc1(Φ1end)=Vc1(Φ2end), and let Vx be the positive node of comparator
===> (Voltage at left plate) - (Voltage at right plate) = Vrefp/4
===> Vip-Vx=Vrefp/4 ===> Vx = Vip-Vrefp/4 .....(1)
cause fully differential, Vy be the negative node of comparator
===> Vy= Vin-Vrefn/4 ....(2)
(1)-(2) ===> Vx-Vy=(Vip-Vin)-(Vrefp-Vrefn)/4
===> Vx-Vy=Vi-Vref/4 ....... (3)

if (3) > 0 ===> Vop=1, Von=0,
else ===> Vop=0, Von=1,

that's it!

 

[snoop835]

Re: Help me to understand Fully Differential Switched Capaci

Thanks Btrend for useful information. Now I gained some understanding and can start working on my design.

CHEERS

Added after 1 hours 24 minutes:

Hi btrend,

I have some more questions to ask!

********************************************************************
at the end of Φ2, Qc1=Vrefp*C, Qc2=0*C, where C1=C, C2=3C
at the start of Φ1, Vc1(Φ2end)=Vc2(Φ2end)==Qc1/(C1+C2)=Vrefp/4
at the end of Φ1, left plate of C1 is at Vip, but there is no path for the charge to leak (assume high impedance), so the charge should contain in the same place as the end of Φ2.
cause Vc1(Φ1end)=Vc1(Φ2end), and let Vx be the positive node of comparator
===> (Voltage at left plate) - (Voltage at right plate) = Vrefp/4
===> Vip-Vx=Vrefp/4 ===> Vx = Vip-Vrefp/4 .....(1)
cause fully differential, Vy be the negative node of comparator
===> Vy= Vin-Vrefn/4 ....(2)
(1)-(2) ===> Vx-Vy=(Vip-Vin)-(Vrefp-Vrefn)/4
===> Vx-Vy=Vi-Vref/4 ....... (3)

if (3) > 0 ===> Vop=1, Von=0,
else ===> Vop=0, Von=1,
********************************************************************

'At the start of Q1, Vc1(Q2end)=Vc2(Q2end)= Qc1/(c1+c2)=Vref/4'
I DON"T QUITE GET THIS! Can you elaborate more!

From my understanding, when Q2 turn off, both Q1 and Q2 will be off for a short while. At this point, voltage drop at C1=Vref/4
voltage drop at C2=3Vref/4
When Q1 start to turn on, positive plate of both capacitors (c1, c2) now are connected at the same potential Vin+. What I understand from your explanation, when positive plate of both capacitors are connected at Vin+, voltage drop at C1=voltage drop at C2= Vref/4. I DONT GET WHY IS THIS HAPPEN?

CHEERS

 

[tuza2000]

it a wonderful explaination,cheers!
it is very helpful for me !

Added after 39 minutes:

snoop835
can you share me the paper you studying?
my email:tuza2000@126.com

 

[jotamario]

Thanks guys for this explanation. I really needed this information too. Do you have a paper for study this? Could you pass me the link? If it is a IEEE paper I have access.

Thanks again.