[SOLVED] Help me to solve the binding prblem in a vhdl program

[Jimcy George]

Hai all,
In this program,i have a run time error.how to solve this?




Library ieee;
Use ieee.std_logic_1164.all;
entity cmp IS
PORT(a,b:IN integer;
c,d:OUT integer);
end;

architecture behaviour of cmp is

begin
process(a,b)
begin
if a<b then
c<=a;
d<=b;
else
c<=b;
d<=a;
end if;
end process;
end;

Library ieee;
Use ieee.std_logic_1164.all;
entity sort IS
PORT(p1,p2,p3:IN integer;
q1,q2,q3:OUT integer);
end;

architecture xsd of sort is
signal c1, c2, c3: integer;

component cmp is
port(a, b: in integer;
c, d: out integer);
end component;

begin

s1:cmp port map(p2, p3, c1, c2);
s2:cmp port map(p1, c1, q1, c3);
s3:cmp port map(c3, c2, q2, q3);

end;

library ieee;
use ieee.std_logic_1164.all;
entity regn is
port(d:in integer;
clk:in std_logic;
qut integer);
end regn;
architecture rtl of regn is
begin
regprocrocess
begin
wait until clk 'event and clk='1';
q<=d after 1 ns;
end process;
end rtl;

library ieee;
use ieee.std_logic_1164.all;
entity pipe is
port(p1,p2,p3,p4,p5,p6,p7,p8,p9:in integer;
clk:in std_logic;
medianut integer);
end pipe;
architecture are of pipe is
signal l1,l2,l3,m1,m2,m3,h1,h2,h3:integer;
signal r1,r2,r3,r4,r5,r6,r7,r8,r9:integer;
signal t1,t2,t3,t4,t5,t6,t7,t8,t9:integer;
signal ll1,mm1,hh,ll2,mm,hh2,ll,mm3,hh3,l0,h0:integer;
component regn
port(d:in integer;
clk:in std_logic;
qut integer);
end component;
component sort
port(p1,p2,p3:in integer;
low,middle,highut integer);
end component;
begin
g1:for y in 1 to 3 generate
g2:if y=1 generate
c3s1:sort port map(p1,p2,p3,l1,m1,h1);
reg10:regn port map(l1,clk,t1);
reg11:regn port map(m1,clk,t2);
reg12:regn port map(h1,clk,t3);
end generate g2;
g3:if y=2 generate
c3s1:sort port map(p4,p5,p6,l2,m2,h2);
reg13:regn port map(t1,clk,t4);
reg14:regn port map(t2,clk,t5);
reg15:regn port map(t3,clk,t6);
reg10:regn port map(l2,clk,t1);
reg11:regn port map(m2,clk,t2);
reg12:regn port map(h2,clk,t3);
end generate g3;
g4:if y=3 generate
c3s1:sort port map(p7,p8,p9,l3,m3,h3);
reg16:regn port map(t4,clk,t7);
reg17:regn port map(t5,clk,t8);
reg18:regn port map(t6,clk,t9);
reg13:regn port map(t1,clk,t4);
reg14:regn port map(t2,clk,t5);
reg15:regn port map(t3,clk,t6);
reg10:regn port map(l3,clk,t1);
reg11:regn port map(m3,clk,t2);
reg12:regn port map(h3,clk,t3);
end generate g4;
end generate g1;

c3s4:sort port map(t7,t4,t1,ll1,mm1,hh);
c3s5:sort port map(t8,t5,t2,ll2,mm,hh2);
c3s6:sort port map(t9,t6,t3,ll,mm3,hh3);

c3s7:sort port map(hh,mm,ll,l0,median,h0);
end are;

 

[yourcheers]

can u post the error message?

 

[Jimcy George]

ELAB2: Fatal Error: ELAB2_0010 dfgd.vhd (47): Signal "q" has multiple sources but is not resolved.
ELAB2: Last instance before error: /g1__2/g3/reg10
KERNEL: Error: E8005 : Kernel process initialization failed.
Fatal error occurred during simulation initialization.

 

[TrickyDicky]

you're connecting the outputs of some of the registers to the outputs of other registers. Because integer is not a resolved type, this is not allowed in VHDL. (even if it was a resolved type, the signal would be 'X')