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Help me to simulate INL and DNL using Cadence

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vijay_nag

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Hi all!

i am trying to simulate INL and DNL using cadence. i tried looking up for the same in the board. but i could not get satisfactory answers. can anybody please explain me in detail about setting test benches, simulation procedure and measurement techniques (everything necessary)?

thanks in advance,
vijay
 

neo

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INL,DNL measurement

i suggest u donnot simulate the static performance, it is a disaster for u, wasting ur time!
 

DenisMark

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INL,DNL measurement

Look for jonathan David (cadence) articles. He have some articles about INL&DNL testbench. He's participiant of edaboard :) I have one article but it's difficult to find it.
 

vijay_nag

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Re: INL,DNL measurement

hi all!

please explain the whole procedure in detail. i have already tried everything i could but i am not able to make any breakthoughs in that regard. i am trying the simulation in cadence. please tell how to go about.

regards,
vijay
 

dumbfrog

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INL,DNL measurement

Check out this book
CMOS Circuit Design, Layout, and Simulation
There are examples in the DA/AD chapter
 

vijay_nag

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Re: INL,DNL measurement

Hi all!

can anybody explain me in detail how to find INL, DNL of a ADC using code density(histogram) method?

regards
vijay
 

renwl

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Re: INL,DNL measurement

vijay_nag said:
Hi all!

can anybody explain me in detail how to find INL, DNL of a ADC using code density(histogram) method?

regards
vijay
You can read the ADC handbook by ADI.
 

vijay_nag

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Re: INL,DNL measurement

renwl said:
You can read the ADC handbook by ADI.
hi renwl!

i tried searching for the document in ADI website but could not find it. could you please upload that document or give me its link?

regards,
vijay
 

renwl

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INL,DNL measurement

Simulating the INL and DNL is not valueable
 

vijay_nag

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Re: INL,DNL measurement

pfd001 said:
Simulating the INL and DNL is not valueable
hi pfd001,

can you tell me how do i measure these errors without simulating in cadence?

then can anybody please tell me how to nullify offset and gain errors at the top level of the ADC? this i need for measuring INL and DNL errors.

regards,
vijay
 

cloudius

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INL,DNL measurement

use verilog-a to sim.those code i found from a post here...icant find link..




// VerilogA for TEST_ADC, inldnlmeasure, veriloga
// $Date: 2005/11/25
// $Revision: 0.0 $
// Static perfomance ADc mesure
// Accuracy depend from dLSB=S*T/LSB
// S -slope of ramp
// T - clock signal period
// LSB - voltage of LSB
// Thow methods of INL measure
// method = 0 - End Point INL
// method = other - Best Fit INL

`include "constants.vams"
`include "disciplines.vams"

`define HIBIT 7
`define HIBIN 1023

module inldnlmeasure (vd,inp,inn);
input [`HIBIT:0] vd;
input inp, inn;
electrical [`HIBIT:0] vd;
electrical inp, inn, vclk;

parameter real vtrans_clk = 2.5; // Threshold
parameter real fullscale = 1.0; // For Gain Error Estimation
parameter integer maxcode = pow(2,`HIBIT); // Number of bins
parameter integer method = 0; // 0 - End Point INL; other - Best Fit INL

real X[`HIBIN:0],Y[`HIBIN:0],dnl[`HIBIN:0],inl[`HIBIN:0];
integer maxcount,count,i;
real measbin,offseterr,gainerr,dnlmax,dnlmin,inlmax,inlmin;
integer dnlout,inlout;
real S,S1,S2,S3,S4,D,D1,D0,A1,A0;

analog begin
@(initial_step) begin
for (i=0;i<`HIBIN;i=i+1) begin
X = 0;
Y = 0;
dnl = 0;
inl = 0;
end
count = 0;
dnlout = $fopen("~/dnlmeasure.dat");
inlout = $fopen("~/inlmeasure.dat");
end

@(cross(V(vd[0]) - vtrans_clk, 0)) begin
X[count] = $abstime;
Y[count] = V(inp,inn);
count = count + 1;
end

@(final_step) begin
maxcount = count;
// Linear Approximation (Best Fit)
S1 = 0; S2 = 0; S3 = 0; S4 = 0;
for (i=0;i<maxcount;i=i+1) begin
S1 = S1 + pow(X,2);
S2 = S2 + X;
S3 = S3 + X*Y;
S4 = S4 + Y;
end
D = S1*maxcount - pow(S2,2);
D1 = S3*maxcount - S2*S4;
D0 = S1*S4 - S2*S3;
A1 = D1/D;
A0 = D0/D;
// LSB Estimation
for (i=1;i<maxcount;i=i+1) begin
S = S + (Y - Y[i-1]);
end
measbin = S/(maxcount - 1);
// Offset, Gain Error Estimation
offseterr = -A0/measbin;
gainerr = (fullscale - maxcode*measbin)/measbin;
// DNL, INL estimation
dnlmax = 0; dnlmin = 0; inlmax = 0; inlmin = 0;
for (i=0;i<=maxcount;i=i+1) begin
// DNL
if (i == 0 || i == maxcount) dnl = 0;
else dnl = (Y-Y[i-1])/measbin-1.0;
if (method == 0) begin
// End points INL
if (i == 0) inl = 0;
else inl = inl[i-1]+dnl;
end else begin
// Best fit INL
if (i == maxcount) inl = 0;
else inl = ((measbin*(i+1.0/2.0)+A0) - Y)/measbin;
end
// Summary
if (dnl>dnlmax) dnlmax = dnl;
if (dnl<dnlmin) dnlmin = dnl;
if (inl>inlmax) inlmax = inl;
if (inl<inlmin) inlmin = inl;
// Write for drawing
$fdisplay(dnlout,"%d\t%10.6f",i,dnl);
$fdisplay(inlout,"%d\t%10.6f",i,inl);
end
$fclose(dnlout);
$fclose(inlout);
// Summaries
$display("Summmary of ADC Static Parameters");
$display("Measure Module:\t%m");
$display("Number of Codes:\t%d",maxcount+1);
$display("Max Offset Error:\t%+.2f",offseterr);
$display("Max Gain Error:\t\t%+.2f",gainerr);
$display("Max DNL:\t\t%+.2f/%+.2f",dnlmin,dnlmax);
$display("Max INL:\t\t%+.2f/%+.2f",inlmin,inlmax);
$display("Plot dnlmeasure.dat & inlmeasure.dat for details...");
end
end
endmodule
`undef HIBIT
 

    vijay_nag

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fazal_ece

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Re: INL,DNL measurement

I am trying to measure INL/DNL for DAC.I am facing problem with MATLAB script of dallas for measuring INL/DNL for ADC in the following.PLs suggest me to get the simulation .

%Code density/histogram test to calculate INL and DNL require a
large number of samples.
%Step 1: Apply a close to full-scale sine wave (but not clipping)
and find the mid-code for the applied signal.
%Step 2: Apply the same sine wave input, but slightly larger
amplitude to clip the ADC slightly.
%Run the following program, enter the number of samples,
resolution and mid-code from Step 1and continue.
%Copyright Au/Hofner, Maxim Integrated Products, 120 San Gabriel
Drive, Sunnyvale, CA94086
www.maxim-ic.com/an2085
Page 7 of 9
%This program is believed to be accurate and reliable. This
program may get altered without prior notification.
filename=input('File Name or press ENTER for Listing Transfer
HP16500C: ');
if isempty(filename)
filename = 'listing';
end
fid=fopen(filename,'r');
numpt=input('Number of Data Points? ');
numbit=input ('ADC Resolution? ');
mid_code=input(Enter Mid-Code (Mean): ');
for i=1:13, %Discard 13 lines of redundant or header-related
HP16500C data
fgetl(fid);
end
[v1,count]=fscanf(fid,'%f',[2,numpt]);
fclose(fid);
v1=v1';
code=v1:),2);
code_count=zeros(1,2^numbit); %Code count
for i=1:size(code),
code_count(code(i)+1)=code_count(code(i)+1) + 1;
end
%Routine to detect whether the ADC's input is clipping or not
if code_count(1) == 0 | code_count(2^numbit) == 0 | ...
(code_count(1) < code_count(2)) | (code_count(2^numbit-1) >
code_count(2^numbit))
disp('Increase Sine-Wave Amplitude to Slightly Clip the
ADC!!!');
break;
end
A=max(mid_code,2^numbit-1-mid_code)+0.1; %Initial estimate of
actual sine wave amplitude
vin=(0:2^numbit-1)-mid_code; %distance of codes to mid code
sin2ramp=1./(pi*sqrt(A^2*ones(size(vin))-vin.*vin));
%sin2ramp*numpt is the expected
%Count each code; keep increasing estimate of A until the actual
total number of counts from
%code 1 to 2^numbit-2 matches with that predicted by
sin2ramp*numpt
while sum(code_count(2:2^numbit-1)) <
numpt*sum(sin2ramp(2:2^numbit-1))
A=A+0.1;
sin2ramp=1./(pi*sqrt(A^2*ones(size(vin))-vin.*vin));
end
disp('You Have Applied a Sine Wave of (dBFS): ');
Amplitude=A/(2^numbit/2)
figure;
plot([0:2^numbit-1],code_count,[0:2^numbit-1],sin2ramp*numpt);
title('CODE HISTOGRAM - SINE WAVE');
xlabel('DIGITAL OUTPUT CODE');
ylabel('COUNTS');
axis([0 2^numbit-1 0 max(code_count(2),code_count(2^numbit-1))]);
code_countn=code_count(2:2^numbit-1)./(numpt*sin2ramp(2:2^numbit-
1)); %End points discarded!
figure;
plot([1:2^numbit-2],code_countn);
title('CODE HISTOGRAM - NORMALIZED')
xlabel('DIGITAL OUTPUT CODE');
ylabel('NORMALIZED COUNTS');
dnl=code_countn-1; %DNL=Vj+1-Vj-1LSB where Vj represents a
transition point
%Vj+1-Vj is proportional to normalized code
count
inl=zeros(size(dnl));
for j=1:size(inl')
inl(j)=sum(dnl(1:j)); %INL,j=DNL,0+DNL,1+...+DNL,j
end
%INL still contains the offset and gain error!
%INL with end-points fit, i.e. INL=0 at end-points the straight
line joining the 2 end points
%[p,S]=polyfit([1,2^numbit-2],[inl(1),inl(2^numbit-2)],1);
%the best-fit straight line
[p,S]=polyfit([1:2^numbit-2],inl,1);
inl=inl-p(1)*[1:2^numbit-2]-p(2);
disp('End Points Eliminated for DNL and INL Calculations');
figure;
plot([1:2^numbit-2],dnl);
grid on;
title('DNL');
xlabel('DIGITAL OUTPUT CODE');
ylabel('DNL (LSB)');
figure;
plot([1:2^numbit-2],inl);
grid on;
title('INL (BEST END-POINT FIT)');
xlabel('DIGITAL OUTPUT CODE');
ylabel('INL(LSB)');

regards,
fazal
 

vijay_nag

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Re: INL,DNL measurement

Hi!

Can we do offset and gain error calculations using code density method?
Theoretically these are measured when we sweep the input voltage.

Regards,
vijay
 

020170

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Re: INL,DNL measurement

I don't know how to measure INL/DNL in Cadence

But if you know some simple C++ coding skill, it is easy to make the program to calculate INL DNL.

maybe, I wish this code was helpful.

Be cautious that code is not perfect
 

vijay_nag

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Re: INL,DNL measurement

020170 said:
I don't know how to measure INL/DNL in Cadence

But if you know some simple C++ coding skill, it is easy to make the program to calculate INL DNL.

maybe, I wish this code was helpful.

Be cautious that code is not perfect
Hi 020170,

I already have the veriloga code which measures INL and DNL using code density method. But i wanted to know whether we can use this method for finding offset and gain error. In theory these are defined where the analog input voltage is swept.

Regards,
Vijay
 

venkats

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Re: INL,DNL measurement

hi vijay.
can u help me in simulating inl and dnl ,sfdr for DAC in cadence.plz help me in this aspect..
thanks
 

vijay_nag

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Re: INL,DNL measurement

venkats said:
hi vijay.
can u help me in simulating inl and dnl ,sfdr for DAC in cadence.plz help me in this aspect..
thanks
Hi venkats,

for inl and dnl calculation of a DAC there are veriloga blocks available in the ahdlLib. these are for 8bit DAC. you can customise them to the resolution of your DAC. after that put the symbol for these blocks in you schematic and simulate. for dynamic testing you will have to go through the document in ADI (the link is posted in the topic).

Regards,
Vijay
 

020170

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Re: INL,DNL measurement

vijay_nag said:
020170 said:
I don't know how to measure INL/DNL in Cadence

But if you know some simple C++ coding skill, it is easy to make the program to calculate INL DNL.

maybe, I wish this code was helpful.

Be cautious that code is not perfect
Hi 020170,

I already have the veriloga code which measures INL and DNL using code density method. But i wanted to know whether we can use this method for finding offset and gain error. In theory these are defined where the analog input voltage is swept.

Regards,
Vijay
Hello Vijay

You can't find gain error and offset error by using my method.

But if you understand perfectly Gain error and offset error, It is not difficult to make a program that find the value of offset error/gain error.

in my thought, gain error and offset error in DAC is not important.

and INL is more important than DNL

Regards,
020170
 

vijay_nag

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Re: INL,DNL measurement

Hi friends,

I have got the INL and DNL errors of the ADC using the code density method. When i do transient simulation for this method no codes are missing. But when i do DC analysis of the design by sweeping the input voltage i find that there are a lot of missing codes. What does this indicate? Does it mean that the code density method is giving wrong results? Can anyone please explain me this discrepency.

Regards,
Vijay
 

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