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# help me to design multpiler in verilog..can give the input only as binary numbers..

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#### diaz080

##### Member level 4
i need to design a multiplier unit..
design idea: only binary inputs representation ..no signed representation..can provide a sign bit input..
ie.. if we want to multiply 2 and -3.. input given should be 0010 and 0011(consider 4 bit numbers)..since sign of one of the number is negative..i can give a sign bit input as 1 here.. so i need a program to make this 0011 input with sign 1 that represents -3 to be converted as 1101 form..
sorry about my language..for better understanding an image is attached..
plz help me..i will upload the work completed till now..postive number multiplication is working good..but having problem with positive and the negative number multiplication

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Code:
// multiplier block
module fun(a,b,c,clk,sign);
input [3:0]a,b;
input [1:0]sign;
input clk;
output reg[7:0]c;
reg [3:0]t=4'd0;
reg [3:0]a1;
reg [3:0]b1;
//wire[1:0]temp;
//assign temp={a[3],b[3]};
reg [7:0]r=7'd0;
wire [4:0]h;
reg [7:0]i;
wire [7:0]i1;
wire [7:0]c1;

//wire n=sign[0]^sign[1];
// twosin t1(.in({1'b1,b[2:0]}),.out(h));
// twosout t2(.in({1'b1,i1[6:0]}),.out(c1));
assign i1=i;
always@(a,b,sign)
begin
r<=0;
t<=0;
end

always @(a,b,posedge clk,sign)
begin

case(sign)
2'b00:
begin
if(t<b)
begin
r=a+r;
c=r;
t=t+1;
end
else
begin
t=0;
r=0;
end
end
2'b01:
begin
// b1=~b+4'd1;
b1=h;
if(t<a)
begin

r=b1+r;
i<=r;
//c=~r+8'd1;
c=c1;
t=t+1;
end
else
begin
t=0;
r=0;
end
end
//2'b10:
//      begin
//
//      a1=~a+4'd1;
//      if(t<b)
//        begin
//
//         r=a1+r;
//          c=~r+8'd1;
//          t=t+1;
//        end
//      else
//        begin
//        t=0;
//        r=0;
//      end
//      end
//      2'b11:
//      begin
//        a1=~a+1;
//        b1=~b+1;
//        if(t<b1)
//          begin
//           r=a1+r;
//          c=r;
//            t=t+1;
//          end
//        else
//          begin
//            r=0;
//          t=0;
//        end
//        end
default: c=0;
endcase
end
endmodule

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the test bench of the top module..
Code:
//test bench
module fun_tb;
reg [3:0]a,b;
reg clk;
reg [1:0]sign;
wire [7:0]c;
fun u1(a,b,c,clk,sign);
always #5 clk=~clk;
initial
begin
clk=1;
sign=2'b00;
a=4'b0101; b=4'b0010;
#100 sign=2'b01; a=4'b0110; b=4'b0011;
end
endmodule

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2s compliment module for 4 bit
Code:
module twosin(in,out);
parameter n=4;
input [n-1:0] in;
output [n-1:0]out;
assign out= ~in+1;
endmodule
.
and for 8 bit
Code:
module twosout(in,out);
parameter n=8;
input [n-1:0] in;
output [n-1:0]out;
assign out= ~in+1;
endmodule

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