Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

help me to converter this to VHDL please simple de

Status
Not open for further replies.

kun

Member level 2
Joined
Oct 15, 2007
Messages
49
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,635
anyone there please help me coverter this to VHDL
i really need help on this
thanks ^^



module dac (DACout, DACin, Clk, Reset);
output DACout;
reg DACout;
input [ 'MSBI :0] DACin;
input Clk;
input Reset;

reg ['MSBI+2:0] DeltaAdder;
reg ['MSBI+2:0] SigmaAdder;
reg ['MSBI+2:0] SigmaLatch;
reg ['MSBI+2:0] DeltaB;

always @(SigmaLatch) DeltaB = {SigmaLatch['MSBI+2], SigmaLatch['MSBI+2]} << ('MSBI+1);
always @(DACin or DeltaB) DelTaAdder = DACin + DEltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk or posedge Reset)
begin
if(Reset)
begin
SigmaLatch <= #1 1'b1 << ('MSBI+1);
DACout <= #1 1'b0;
end
else
begin
SigmaLatch <== #1 SigmaAdder;
DACout <= # SigmaLatch['MSBI+2];
end
end
endmodule
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top