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Help me solve the error in the code!

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brahma

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what is the problem?

BEGIN
process
begin
if s1 ='0' and s2 ='0' then
q1: ask port map(x1,y1,c1); ( i get error)
else if s1 ='0' and s2 ='1' then
q2: askdemod port map(x,y,c); ( error)
end if;
end process;

in this code i get error.
"gp.vhd",line 66: Error, syntax error near 'process'.
"grouping_gp.vhd",line 59: Error, syntax error near 'port'.

i use modelsim simulator, i dont know how to solve this error can anyone help me??
 

bbgil

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Re: what is the problem?

for one, i think you syntax of else if should be elsif. Another check your port mapping syntax. Iam not sure about ask command. hope this help.
 

gliss

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what is the problem?

It doesn't appear 'ask' is valid VHDL. You might want to post the entire module you are tyring to compile.
 

tkbits

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Re: what is the problem?

I don't think you can create components within a process.

If these are functions you're trying to embed, then you probably need to put the functions in a package and use function calls, rather than instantiation syntax.
 

brahma

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Re: what is the problem?

1. bbgil- i also tried elsif i got the same problem

2. gliss-'ask' is not a command word in VHDL i've done port mapping. 'ask' is the entity name where i've mapped to.

3. tkbits-i tried without that process command, no change, same problem exists.[/quote]
 

tkbits

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Re: what is the problem?

And you can't use if outside a process.

What are you trying to accomplish by instantiating within an if? Entities don't "inline".
 

brahma

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Re: what is the problem?

the thing i've done is i've written two different code one for ask and another for askdemod, if the select lines s1 and s2 are 0 then ask has to be called (i.e. portmap) else askdemod has to be called. this is what i want. am i clear to u???
 

sree205

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what is the problem?

hi, shouldn't there be a sensitivity list for the process ?
 

sanjana

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Re: what is the problem?

hi
why don't u try to use "generate" statement.
It works well in the process.

Added after 22 minutes:

otherwise U instantiate the components outside the process statement.Assign the signals in the process block.Use enable signal to select ur components. that will do.
 

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