Designed a ring VCO using 0.18um CMOS process. The simulation tool is Hsp!ce. When measuring many different cycles (using .me@suRe statement), it was found that the durations per cycle were always changing. The design target is 1.140ns per cycle (about 877MHz), but the output varys from 1.138ns to 1.148ns. Anybody here can help me to reduce this variation of the VCO output?
The temperature is fixed, default 27 degrees. The process model is typical and is fixed in the simulation, so the variation of the output waveform doesn't result from the model changing from 'slow' to 'fast'. And the power supply is also fixed. In a short, all conditions are fixed including the control voltage of the VCO. I want to know why there is variation in the output waveform and how to solve the problem
I think two reasons:
1 spice issue .tran resolution usually spice decides it however nSEC area u may touch 0.1nS some preference affects resolution for examples the reltol shall be less than 1/100 of your control voltage range.
2 if ur Vcc or Vss(gnd) line has some resistor caused from metal wireing,it will affect to time constant of ring
pls check
i have design vco for low voltage supply (target 2.0v) using 0.18u technology using software mentor graphis.. problem is when ii supply voltage 2.0v the circuit can running (no output)... anybody here can help me to solve this problem?
Added after 1 minutes:
anybody in this forum can suggest to me website or where else i can get information about VCO..