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# Help me out with a cross clock domain design

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#### EDA_hg81

In my design, a local clock is generated by a clock divider, which looks like follow:

process ( iARM7_CLK )
begin
if ( rising_edge( iARM7_CLK ) ) then
spiclkcon <= spiclkcon + 1;
if ( spiclkcon = spiclk_gen ) then
spiclkcon <= x"00";
spiclk <= not spiclk;
elsif ( spiclkcon = x"32" and spiclk = '0' ) then
.. check the data from ARM7 CLOCK domain…
But I have to capture data generated in ARM7_CLOCK domain and have to send data back to ARM7 clock domain.

My question is:

What is the proper way to do those ideas? What I should do to keep those data are valid when they transfer clock domain.

I can not use buffer which is driven by two clocks.

Thanks.

#### shawndaking

##### Full Member level 3
Re: Cross clock domain

whato you should do is keep using your , let's call it system clock, and the use your devided clock as clock enable.

if risinge_edge(sys_clk) then

if divide_clk = '1' then
(

)

your outputs are now aligned with system clock.
pay attentio your outputs to your domain are now allign with sys_clk, and not divide_clk. so you need to shift them.

### EDA_hg81

Points: 2

#### Iouri

Cross clock domain

it is not really CDC since you using only one clock to produce divided clock, both of those clocks will be in same phace.

CDC means when you are crossing domain between two clocks and there is no any relationship between those clocks

### EDA_hg81

Points: 2

#### EDA_hg81

Re: Cross clock domain

Code:
if ( rising_edge( iARM7_CLK  ) ) then
spiclkcon <= spiclkcon + 1;
if ( spiclkcon = spiclk_gen ) then
spiclkcon <= x"00";
spiclk    <= not spiclk;
elsif (  spiclkcon = x"05" and  spiclk = '0' ) then
when x"00" =>
if (  iSD_BUF(7) = '1' ) then
command <= command09;
elsif (  iSD_BUF(6) = '1' )then
command <= command09;
end if;

Do you think code like above is right?

#### Iouri

Cross clock domain

looks about right, but I was told you before, you should separate your processes, make code more readble, and also make compilier job easy. Also when you read your timing report, it makes more easy to analyze when you have more structured code

good lack

### EDA_hg81

Points: 2

#### EDA_hg81

Re: Cross clock domain

Thank you all for help.

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