if sync_counter = 100 then
if sync_edge_count = 0 then
fram_send_slot0 <= X"E000";
elsif sync_edge_count = 1 then
fram_send_slot0 <= X"E000";
else
fram_send_slot0 <= X"C000";
end if;
end if;
if sync_counter = 100 then
if sync_edge_count = 0 then
fram_send_slot0 <= X"E000";
elsif sync_edge_count = 1 then
fram_send_slot0 <= X"E000";
else
fram_send_slot0 <= X"C000";
end if;
end if;
if sync_counter = 100 then
if sync_edge_count = 0 then
fram_send_slot0 <= X"E000";
elsif sync_edge_count = 1 then
fram_send_slot0 <= X"E000";
else
fram_send_slot0 <= X"C000";
end if;
else
fram_send_slot0 <= X"0000";
end if;
if sync_counter = 100 then
if sync_edge_count = 0 then
fram_send_slot0 <= X"E000";
elsif sync_edge_count = 1 then
fram_send_slot0 <= X"E000";
else
fram_send_slot0 <= X"C000";
end if;
else
fram_send_slot0 <= fram_send_slot0;
end if;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity AC97 is
port ( rst, clk : in std_logic;
bit_clk : in std_logic;
sdata_in : in std_logic;
sdata_out : out std_logic;
sync, clk1 : out std_logic);
end AC97;
architecture Behavioral of AC97 is
signal delay_count : integer range 0 to 127;
signal delay_gen : std_logic;
signal sync_s : std_logic;
signal sync_counter : integer range 0 to 255;
signal sync_edge_count : integer range 0 to 15;
signal check_ready : std_logic;
signal ff1, ff2 : std_logic;
signal fram_cap_en : std_logic;
signal end_of_slot : std_logic;
signal bit_counter : integer range 0 to 32;
signal slot_counter : integer range 0 to 15;
---------------------------------------------
-- serial input signals related sdata_in
signal fram_capt : std_logic_vector(19 downto 0);
signal fram_slot0 : std_logic_vector(15 downto 0);
signal fram_slot1 : std_logic_vector(19 downto 0);
signal fram_slot2 : std_logic_vector(19 downto 0);
signal fram_slot3 : std_logic_vector(19 downto 0);
signal fram_slot4 : std_logic_vector(19 downto 0);
signal fram_slot0_tap : std_logic;
----------------------------------------------
-- serial out signals related to sdata_out
signal fram_send : std_logic_vector(19 downto 0);
signal fram_send_slot0 : std_logic_vector(15 downto 0);
signal fram_send_slot1 : std_logic_vector(19 downto 0);
signal fram_send_slot2 : std_logic_vector(19 downto 0);
signal fram_send_slot3 : std_logic_vector(19 downto 0);
signal fram_send_slot4 : std_logic_vector(19 downto 0);
-----------------------------------------------
signal com_mode : std_logic;
signal clk_div : std_logic_vector(23 downto 0);
begin
process(rst, bit_clk)
begin
if rst = '0' then
clk_div <= (others => '0');
elsif rising_edge(bit_clk) then
clk_div <= clk_div + 1;
end if;
end process;
clk1 <= clk_div(23);
--delay generator
process(rst, bit_clk)
begin
if rst = '0' then
delay_count <= 0;
elsif rising_edge(bit_clk) then
if delay_count /= 126 then
delay_count <= delay_count +1;
end if;
end if;
end process;
delay_gen <= '0' when delay_count /= 126 else
'1';
-- sync generator
process(rst, bit_clk)
begin
if rst = '0' then
sync_counter <= 0;
elsif rising_edge(bit_clk) then
if delay_gen = '1' then
sync_counter <= sync_counter + 1;
end if;
end if;
end process;
sync <= sync_s;
sync_s <= '1' when sync_counter >= 1 and sync_counter <= 16 else
'0';
fram_cap_en <= '1' when sync_counter > 1 else
'0';
-- check ready
process(rst, bit_clk)
begin
if rst = '0' then
check_ready <= '0';
elsif rising_edge(bit_clk) then
if fram_slot0_tap = '1' then
check_ready <= '1';
else
check_ready <= '0';
end if;
end if;
end process;
fram_slot0_tap <= fram_slot0(15);
-- Frame Capture
process(rst, bit_clk)
begin
if rising_edge(bit_clk) then
fram_capt <= fram_capt(18 downto 0)& sdata_in;
end if;
end process;
process(bit_clk)
begin
if rising_edge(bit_clk) then
if (bit_counter = 0)then
if slot_counter = 1 then
fram_slot0 <= fram_capt( 15 downto 0);
elsif slot_counter = 2 then
fram_slot1 <= fram_capt;
elsif slot_counter = 3 then
fram_slot2 <= fram_capt;
elsif slot_counter = 4 then
fram_slot3 <= fram_capt;
elsif slot_counter = 5 then
fram_slot4 <= fram_capt;
end if;
end if;
end if;
end process;
-------------------------------------
end_of_slot <= '1' when ((slot_counter = 0 and bit_counter = 15) or bit_counter = 19) else
'0';
process(rst, bit_clk)
begin
if rst = '0' then
slot_counter <= 0;
elsif rising_edge(bit_clk) then
if sync_counter < 1 then
slot_counter <= 0;
else
if slot_counter = 12 then
slot_counter <= 0;
else
slot_counter <= slot_counter + 1;
end if;
end if;
end if;
end process;
process(rst, bit_clk)
begin
if rst = '0' then
bit_counter <= 0;
elsif rising_edge(bit_clk) then
if ( sync_counter < 1 or end_of_slot = '1') then
bit_counter <= 0;
else
bit_counter <= bit_counter + 1;
end if;
end if;
end process;
-------------------------------------------------------------------
-- fram_gen
process (rst, bit_clk)
begin
if rst = '0' then
fram_send <= (others => '0');
elsif rising_edge(bit_clk) then
if end_of_slot = '1' then
case slot_counter is
when 12 => -- slot 0
fram_send <= fram_send_slot0 & "0000";
when 0 => -- slot 1
fram_send <= fram_send_slot1;
when 1 =>
fram_send <= fram_send_slot2;
when 2 =>
fram_send <= fram_send_slot3;
when 3 =>
fram_send <= fram_send_slot4;
when others =>
fram_send <= (others => '0');
end case;
else
fram_send <= fram_send(18 downto 0) & '0';
end if;
end if;
end process;
--process(rst,sync_s)
--begin
-- if rst = '0' then
-- fram_send <= (others =>'0');
-- elsif rising_edge(sync_s)then
-- fram_send <= fram_send_slot0 & fram_send_slot1 & fram_send_slot2 & fram_send_slot3 & fram_send_slot4 & bit_stuff;
-- end if;
--end process;
-- SDATA_OUT
sdata_out <= fram_send(19);
-- sync_edge counter
process(rst, sync_s, check_ready)
begin
if rst = '0' then
sync_edge_count <= 0;
elsif rising_edge(sync_s) and check_ready = '1' then
if sync_edge_count /= 8 then
sync_edge_count <= sync_edge_count + 1;
end if;
end if;
end process;
com_mode <= '1' when sync_edge_count >= 1 and sync_edge_count <= 7 else
'0';
-- process(sync_counter, sync_edge_count, fram_slot3, fram_slot4, fram_send_slot0, fram_send_slot1, fram_send_slot2, fram_send_slot3, fram_send_slot4)
process (bit_clk)
begin
if sync_counter = 100 then
if sync_edge_count = 0 then
fram_send_slot0 <= X"E000";
fram_send_slot1 <= X"00000";
fram_send_slot2 <= X"0D400";
fram_send_slot3 <= X"00000";
fram_send_slot4 <= X"00000";
elsif sync_edge_count = 1 then
fram_send_slot0 <= X"E000";
fram_send_slot1 <= X"02000"; --Master Volume
fram_send_slot2 <= X"00000"; --Full Volume
fram_send_slot3 <= X"00000";
fram_send_slot4 <= X"00000";
elsif sync_edge_count = 2 then
fram_send_slot0 <= X"E000";
fram_send_slot1 <= X"10000"; --Line IN Volume
fram_send_slot2 <= X"00000";
fram_send_slot3 <= X"00000";
fram_send_slot4 <= X"00000";
elsif sync_edge_count = 3 then
fram_send_slot0 <= X"E000";
fram_send_slot1 <= X"18000"; -- PCM Volume
fram_send_slot2 <= X"00000";
fram_send_slot3 <= X"00000";
fram_send_slot4 <= X"00000";
elsif sync_edge_count = 4 then
fram_send_slot0 <= X"E000";
fram_send_slot1 <= X"1A000"; --Record Select --> LINE_IN
fram_send_slot2 <= X"04040";
fram_send_slot3 <= X"00000";
fram_send_slot4 <= X"00000";
elsif sync_edge_count = 5 then
fram_send_slot0 <= X"E000";
fram_send_slot1 <= X"1C000"; --Record Gain
fram_send_slot2 <= X"0F0F0";
fram_send_slot3 <= X"00000";
fram_send_slot4 <= X"00000";
elsif sync_edge_count = 6 then
fram_send_slot0 <= X"E000";
fram_send_slot1 <= X"20000"; --General Register
fram_send_slot2 <= X"00000";
fram_send_slot3 <= X"00000";
fram_send_slot4 <= X"00000";
elsif sync_edge_count = 7 then
fram_send_slot0 <= X"C000";
fram_send_slot1 <= X"00000";
fram_send_slot2 <= X"00000";
fram_send_slot3 <= fram_slot3(19 downto 2)& "00";
fram_send_slot4 <= fram_slot4(19 downto 2)& "00";
else
fram_send_slot0 <= fram_send_slot0;
fram_send_slot1 <= fram_send_slot1;
fram_send_slot2 <= fram_send_slot2;
fram_send_slot3 <= fram_send_slot3;
fram_send_slot4 <= fram_send_slot4;
end if;
end if;
end process;
end Behavioral;
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